Datasheet

ADP1046A Data Sheet
Rev. 0 | Page 56 of 88
Table 41. Register 0x29—Share Bus Bandwidth
Bits Bit Name R/W Description
[7:5] Reserved R/W Reserved.
4 Bit stream R/W 1 = the current sense ADC reading is output on the SHAREo pin. This bit stream can be used for
analog current sharing.
0 = the digital share bus signal is output on the SHAREo pin. This signal can be used for digital
current sharing.
3 Current share
enable
R/W 1 = Reserved.
0 = CS2 reading used for current share.
[2:0] Share bus
bandwidth
R/W These bits determine the amount of bandwidth dedicated to the share bus. A value of 000 is the lowest
possible bandwidth, and a value of 111 is the highest possible bandwidth. The slave is incremented
by 1 LSB per share bus transaction (eight data bits plus start and stop bits). The master is decremented
by N LSBs per share bus transaction, where N is the value of Register 0x2A[7:4].
Bit 2 Bit 1 Bit 0 Bandwidth
0 0 0 Divide LSB by 16, that is, 1 LSB = 24 µV/16
0 0 1 Divide LSB by 8
0 1 0 Divide LSB by 4
0 1 1 Divide LSB by 2
1 0 0 Nominal
1 0 1 Multiply LSB by 2
1 1 0 Multiply LSB by 4
1 1 1 Multiply LSB by 8
Table 42. Register 0x2A—Share Bus Setting
Bits Bit Name R/W Description
[7:4] Number of bits
dropped by master
R/W These bits determine how much a master device reduces its output voltage to maintain current
sharing. For more information, see the description of Bits[2:0] in Register 0x29.
[3:0] Bit difference
between master
and slave
R/W These bits determine how closely a slave tries to match the current of the master device. The
higher the setting, the larger the voltage difference that satisfies the current sharing criteria.
Table 43. Register 0x2B—Temperature Gain Trim
Bits
Bit Name
R/W
Description
7 Gain polarity R/W 1 = negative gain is introduced.
0 = positive gain is introduced.
[6:0] Gain trim R/W This register calibrates the RTD ADC gain. It calibrates for errors in the ADC.
Table 44. Register 0x2C—PSON/Soft Start
Bits Bit Name R/W Description
[7:6] PS_ON setting R/W These bits determine which signal is used by the ADP1046A as the PS_ON control.
Bit 7
Bit 6
PS_ON Setting
0 0 The ADP1046A is always on.
0 1 Hardware PSON pin is used to enable or disable the power supply.
1 0 Software PS_ON bit (Bit 5) is used to enable or disable the power supply.
1 1 Both the software PS_ON bit and the hardware PSON pin must be enabled
before the ADP1046A is enabled.
5 PS_ON R/W Software PS_ON bit.
0 = power supply off.
1 = power supply on.
[4:3] PS_ON delay R/W These bits set the time from when the PS_ON control signal is set to when the soft start begins.
Bit 4 Bit 3 Typical Delay (sec)
0 0 0
0
1
0.5
1 0 1
1 1 2