Datasheet

Data Sheet ADP1046A
Rev. 0 | Page 51 of 88
Register 0x0F allows the user to program the ADP1046A to ignore the specified flags until the end of the soft start ramp time. The UVP
and ACSNS flags are always active during soft start.
Table 15. Register 0x0F—Soft Start Blank Fault Flags Register
Bits Bit Name R/W Description
7 Blank SR R/W Setting this bit means that the SR1 and SR2 PWM outputs are not enabled until the end of the soft
start ramp time.
6
Blank OTP
R/W
Setting this bit means that the OTP flag is ignored until the end of the soft start ramp time.
5 Blank FLAGIN R/W Setting this bit means that the FLAGIN flag is ignored until the end of the soft start ramp time.
4 Blank local OVP
(accurate and fast)
R/W Setting this bit means that the local OVP flag is ignored until the end of the soft start ramp time.
3 Blank load OVP R/W Setting this bit means that the load OVP flag is ignored until the end of the soft start ramp time.
2 Blank CS2 accurate
OCP
R/W Setting this bit means that the CS2 accurate OCP flag is ignored until the end of the soft start
ramp time.
1 Blank CS1 accurate
OCP
R/W Setting this bit means that the CS1 accurate OCP flag is ignored until the end of the soft start
ramp time.
0 Blank CS1 fast OCP R/W Setting this bit means that the CS1 fast OCP flag is ignored until the end of the soft start ramp time.
VALUE REGISTERS
Table 16. Register 0x10—First Flag ID
Bits Bit Name R/W Description
[7:4] Reserved R Reserved.
[3:0] First flag ID R
These bits record the flag that was set first. Restarting the power supply resets this register. Reading
this register also resets the register.
Bit 3
Bit 2
Bit 1
Bit 0
Fault Register
Flag
0 0 0 0 None No flag
0 0 0 1 Register 0x01, Bit 3 VCORE OV
0 0 1 0 Register 0x01, Bit 2 VDD OV
0 0 1 1 Register 0x03, Bit 1 EEPROM CRC fault
0 1 0 0 Register 0x00, Bit 2 CS1 fast OCP
0 1 0 1 Register 0x00, Bit 1 CS1 accurate OCP
0 1 1 0 Register 0x00, Bit 0 CS2 accurate OCP
0 1 1 1 Register 0x01, Bit 1 Load OVP
1 0 0 0 Register 0x01, Bit 0 Local OVP (fast and accurate)
1 0 0 1 Register 0x02, Bit 0 FLAGIN
1 0 1 0 Register 0x02, Bit 7 OTP
1 0 1 1 Register 0x01, Bit 6 UVP
1
1
0
0
Register 0x01, Bit 5
CS2 reverse current
1 1 0 1 Register 0x01, Bit 7 Voltage continuity
1 1 1 0 Register 0x02, Bit 5 Share bus
1 1 1 1 Register 0x03, Bit 2 ACSNS
Table 17. Register 0x11—RTD Current Source
Bits
Bit Name
R/W
Description
[7:6] RTD current setting R/W These bits set the size of the current source on the RTD pin.
Bit 7 Bit 6 Current Source (µA)
0 0 10
0 1 20
1 0 30
1 1 40
[5:0] Current trim R/W These six bits are used to trim the current source on the RTD pin. Each LSB corresponds to 160 nA,
independent of the RTD current setting selected in Register 0x11[7:6].