Datasheet

ADP1046A Data Sheet
Rev. 0 | Page 4 of 88
SPECIFICATIONS
V
DD
= 3.0 V to 3.6 V, T
A
= −40°C to +125°C, unless otherwise noted. FSR = full-scale range.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY
Supply Voltage V
DD
4.7 µF capacitor connected to AGND 3.0 3.3 3.6 V
Supply Current I
DD
Normal operation (PSON is high or low) 20 mA
During EEPROM programming (40 ms) I
DD
+ 8 mA
Shutdown (V
DD
below UVLO) 100 µA
POWER-ON RESET
Power-On Reset V
DD
rising 3.0 V
UVLO V
DD
falling 2.75 2.85 2.97 V
UVLO Hysteresis 40 mV
OVLO
3.8
4.0
4.1
V
OVLO Debounce When set to 2 µs 2.0 µs
When set to 500 µs 500 µs
VCORE PIN 0.33 µF capacitor connected to DGND
Output Voltage T
A
= 25°C 2.4 2.5 2.7 V
OSCILLATOR AND PLL
PLL Frequency RES = 10 kΩ (±0.1%) 190 200 210 MHz
OUTA, OUTB, OUTC, OUTD,
OUTAUX, SR1, SR2, GATE PINS
Output Low Voltage V
OL
Source current = 10 mA 0.4 V
Output High Voltage V
OH
Source current = 10 mA V
DD
− 0.4 V
Rise Time C
LOAD
= 50 pF 3.5 ns
Fall Time C
LOAD
= 50 pF 1.5 ns
VS1, VS2, VS3 LOW SPEED ADCs
Input Voltage Range V
IN
Differential voltage from VS1, VS2 to
PGND, and from VS3+ to VS3−
0 1 1.6 V
Usable Input Voltage Range 0 1.4 V
ADC Clock Frequency 1.56 MHz
Register Update Rate 10 ms
Voltage Sense Measurement
Accuracy
Factory trimmed at 1.0 V
0% to 100% of usable input voltage range −3.0 +3.0 % FSR
−48
+48
mV
10% to 90% of usable input voltage range −2.0 +2.0 % FSR
−32 +32 mV
900 mV to 1.1 V −1.0 +1.0 % FSR
−16 +16 mV
Temperature Coefficient
65
ppm/°C
Leakage Current
1.0
µA
Voltage Sense Measurement
Resolution
12 Bits
Common-Mode Voltage Offset −0.25 +0.25 % FSR
Voltage Differential from VS3−
to PGND
−200 +200 mV
VS1 Accurate OVP Speed Register 0x32[1:0] = 00; equivalent
resolution is 7 bits
80 µs
VS1 OVP Threshold Accuracy Relative to nominal voltage (1 V) on VS1 −2.0 +2.0 % FSR
VS2 and VS3 OVP Speed Register 0x33[1:0] = 00; equivalent
resolution is 7 bits
80 µs
VS2 and VS3 OVP Threshold
Accuracy
Relative to nominal voltage (1 V) on VS2
and VS3
−2.0
+2.0
% FSR