Datasheet

ADP1046A Data Sheet
Rev. 0 | Page 38 of 88
Command Overview
Data transfer using the I
2
C slave is established using commands.
All commands start with a slave address with the R/
W
bit cleared
(set to 0), followed by the command code (register address). All
commands supported by the ADP1046A follow one of the protocol
types shown in Figure 47 to Figure 53.
S
7-BIT SLAVE
ADDRESS
W
A A
P
COMMAND CODE
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
11012-141
Figure 47. Send Byte Protocol
S
7-BIT SLAVE
ADDRESS
W A A A P
COMMAND
CODE
DATA
BYTE
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
11012-142
Figure 48. Write Byte Protocol
S
7-BIT SLAVE
ADDRESS
W A
A
DATA
BYTE
HIGH
COMMAND
CODE
DATA
BYTE
LOW
A A P
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
11012-143
Figure 49. Write Word Protocol
DATA BYTE NA P
S
7-BIT SLAVE
ADDRESS
W A A
7-BIT SLAVE
ADDRESS
COMMAND
CODE
Sr R A
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
11012-144
Figure 50. Read Byte Protocol
DATA BYTE LOW A NA
PDATA BYTE HIGH
S
7-BIT SLAVE
ADDRESS
W A A
7-BIT SLAVE
ADDRESS
COMMAND
CODE
Sr R A
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
11012-145
Figure 51. Read Word Protocol
DATA BYTE 1 A ... A PDATA BYTE N
S
7-BIT SLAVE
ADDRESS
W A A
BYTE
COUNT = N
COMMAND
CODE
A
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
11012-146
Figure 52. Block Write Protocol
S
7-BIT SLAVE
ADDRESS
7-BIT SLAVE
ADDRESS
W
A
A
COMMAND
CODE
A
R
Sr
DATA
BYTE 1
A
A ...
NA
DATA
BYTE N
P
BYTE
COUNT = N
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
11012-147
Figure 53. Block Read Protocol
Clock Generation and Stretching
The ADP1046A is always a slave in the overall system; therefore,
the device never needs to generate the clock, which is done by
the master device in the system. However, the I
2
C slave device is
capable of clock stretching to place the master in a wait state. By
stretching the SCL signal during the low period, the slave device
communicates to the master device that it is not ready and that
the master device must wait.
Conditions where the I
2
C slave device stretches the SCL line low
include the following:
• The master device is transmitting at a higher baud rate
than the slave device.
• The receive FIFO buffer of the slave device is full and must
be read before continuing. This prevents a data overflow
condition.
• The slave device is not ready to send data that the master
has requested.
Note that the slave device can stretch the SCL line only during
the low period. Also, whereas the I
2
C specification allows indefinite
stretching of the SCL line, the ADP1046A limits the maximum
time that the SCL line can be stretched, or held low. For more
information about the maximum time, see the Timeout
Condition section.
Start and Stop Conditions
Start and stop conditions involve serial data transitions while the
serial clock is at a logic high level. The I
2
C slave device monitors
the SDA and SCL lines to detect the start and stop conditions
and transition its internal state machine accordingly. Typical
start and stop conditions are shown in Figure 54.
SCL
SDA
START
STOP
11012-148
Figure 54. Start and Stop Transitions