Datasheet

ADP1046A Data Sheet
Rev. 0 | Page 36 of 88
LAYOUT GUIDELINES
This section explains best practices that should be followed
to ensure optimal performance of the ADP1046A. In general,
place all components as close to the ADP1046A as possible.
All signals should be referenced to their respective grounds.
CS2+ AND CS2−
Route the traces from the sense resistor to the ADP1046A
parallel to each other. Keep the traces close together and as
far from the switch nodes as possible.
VS3+ AND VS3−
Route the traces from the remote voltage sense point to the
ADP1046A parallel to each other. Keep the traces close together
and as far from the switch nodes as possible. Place a 100 nF capac-
itor from VS3− to AGND to reduce common-mode noise.
VDD
Place the decoupling capacitors as close to the part as possible.
A 4.7 µF capacitor from VDD to AGND is recommended.
SDA AND SCL
Route the traces to these pins parallel to each other. Keep the
traces close together and as far from the switch nodes as possible.
CS1
Route the traces from the current sense transformer to the
ADP1046A parallel to each other. Keep the traces close together
and as far from the switch nodes as possible.
EXPOSED PAD
Solder the exposed pad underneath the ADP1046A to the PCB
AGND plane.
VCORE
Place a 330 nF decoupling capacitor from this pin to DGND as
close to the part as possible.
RES
Place a 10 kΩ, ±0.1% resistor from this pin to AGND as close to
the part as possible.
RTD
Route a single trace to the ADP1046A from the thermistor using
a dedicated trace to AGND. Place the thermistor close to the
hottest part of the power supply.
AGND, DGND, AND PGND
Create an AGND ground plane and make a single-point (star)
connection to the power supply system ground. Connect DGND to
AGND with a very short trace using a star connection. Connect
PGND to AGND using a star connection.