Datasheet

ADP1046A Data Sheet
Rev. 0 | Page 32 of 88
VOLT-SECOND BALANCE
The ADP1046A has a dedicated circuit to maintain volt-second
balance in the main transformer when operating in full-bridge
topology. This circuit eliminates the need for a dc blocking capac-
itor. In interleaved topologies, volt-second balance can also be
used for current balancing to ensure that each interleaved phase
contributes equal power.
The circuit monitors the current flowing in both legs of the full-
bridge topology and stores this information. It compensates the
selected PWM signals to ensure equal current flow in both legs
of the full-bridge topology. The input is through the CS1 pin.
Several switching cycles are required for the circuit to operate
effectively. The maximum amount of modulation applied to
each edge of the selected PWM outputs is programmable to
±80 ns or ±160 ns in Register 0x28[2].
The volt-second balance settings are programmed in Register 0x28
and in Register 0x76 through Register 0x78. It is recommended
that the Analog Devices software GUI be used to program these
settings.
The compensation of the PWM drive signals is performed on
the edges of two selected outputs. The SR1 and SR2 edges can
also be independently set to modulate due to the volt-second
balance circuit to maintain the timing relation to the primary
side signals.
DIGITAL LOAD LINE AND SLEW RATE
The ADP1046A can optionally introduce a digital load line into
the power supply. This option is programmed in the load line
impedance register (Register 0x36). Two parameters can be
configured independently: slew rate and load line value.
The slew rate (Register 0x36[6:4]) determines how quickly the
output voltage is adjusted in response to a change in the digital
reference. Eight different settings are available.
The load line value (Register 0x36[2:0]) controls the slope of
the load line. The amount of output resistance introduced can
be calculated as follows:
R
OUT
= 0.1 × V
OUT_NOM
× CS2 R
SENSE
/(CS2 Range × 2
LOAD_SET[2:0]
)
where:
V
OUT_NOM
is the nominal output voltage when VS3 = 1 V.
CS2 R
SENSE
is the sense resistor value.
CS2 Range is 120 mV or 60 mV.
LOAD_SET[2:0] is the value of Bits[2:0] in Register 0x36
(0 to 7 decimal).
For example, if V
OUT_NOM
= 12 V, CS2 R
SENSE
= 10 mΩ,
CS2 Range = 120 mV, and LOAD_SET[2:0] = 3,
R
OUT
= 0.1 × 12 V × 10 mΩ/(120 mV × 2
3
) = 12.5 mΩ
This feature can be used for advanced current sharing techniques.
By default, the load line is disabled. The load line is introduced
digitally by modifying the value of the digital reference based
on the CS2 reading.
Figure 43 and Figure 44 show the load line as a percentage of
V
OUT
vs. the R
SENSE
voltage drop.
100
90
91
92
93
94
95
96
97
98
99
0 20 40 60 80 100 12010 30 50 70 90 110
V
OUT
(%)
R
SENSE
VOLTAGE DROP (mV)
SETTING 7
SETTING 6
SETTING 5
SETTING 4
SETTING 3
SETTING 2
SETTING 1
SETTING 0
11012-030
Figure 43. Load Line Settings with 120 mV CS2 Range
100
88
90
92
94
96
98
0 1020304050605 1525354555
V
OUT
(%)
R
SENSE
VOLTAGE DROP (mV)
SETTING 7
SETTING 6
SETTING 5
SETTING 4
SETTING 3
SETTING 2
SETTING 1
SETTING 0
11012-031
Figure 44. Load Line Settings with 60 mV CS2 Range