Datasheet

Data Sheet ADP1046A
Rev. 0 | Page 21 of 88
OrFET ENABLE
UVP
t
0
PSON
VS3
VS1
(VS1 – VS2)
VOLTAGE
OrFET GATE
LOOP CONTROLLED
FROM VS1
LOOP CONTROLLED
FROM VS3
UVP FLAG
PGOOD1
PS_ON DELAY
(REG 0x2C[4:3])
RAMP TIME
(REG 0x5F[7:5])
PGOOD DEBOUNCE
(REG 0x2D)
11012-120
Figure 24. Soft Start Timing Diagram
PSON
V
OUT
RAMP TIME
(REG 0x5F[7:5])
12.5% REF
LIGHT LOAD
FILTER (LLF)
NORMAL MODE FILTER (NMF)
OR SOFT START FILTER (SSF)
NORMAL MODE FILTER (NMF)
OR SOFT START FILTER (SSF)
LLF OR NMF
BASED ON
LOAD
LLF OR NMF
BASED ON
LOAD
11012-121
NORMAL MODE FILTER (NMF)
OR SOFT START FILTER (SSF)
Figure 25. Filter Sequencing at Startup