Datasheet

ADP1046A Data Sheet
Rev. 0 | Page 16 of 88
VOLTAGE SENSE AND CONTROL LOOP
Multiple voltage sense inputs on the ADP1046A are used for the
monitoring, control, and protection of the power supply output.
This information is available through the I
2
C interface. All voltage
sense points can be calibrated digitally to minimize errors due to
external components. This calibration can be performed in the
production environment, and the settings can be stored in the
EEPROM of the ADP1046A (see the Power Supply Calibration
and Trim section for more information).
For voltage monitoring, the VS1, VS2, and VS3 voltage value
registers (Register 0x15, Register 0x16, and Register 0x17,
respectively) are updated every 10 ms. The ADP1046A stores
every ADC sample for 10 ms and then outputs the average value
at the end of the 10 ms period. Therefore, if these registers are
read at least every 10 ms, a true average value is read.
The ADP1046A uses two separate sensing points: VS1 and VS3±,
depending on the condition of the OrFET. When the OrFET is
turned off, the control loop is regulated via VS1; when the OrFET
is turned on, the control loop is regulated via the differential
sensing on VS3±. This sensing mechanism effectively performs
a local and remote voltage sense.
The control loop of the ADP1046A features a patented multi-
path architecture. The output voltage is converted simultaneously
by two ADCs: a high accuracy ADC and a high speed ADC. The
complete signal is reconstructed and processed in the digital
filter to provide a high performance, cost competitive solution.
VS1
VS3+
VS3–
VS2
ADC
PGND
VS3VS2
12 BITS
VS1
12 BITS
DIGITAL
FILTER
1V 1V
12V 12V
11kΩ
1kΩ
1V
LOAD
11kΩ11kΩ
1kΩ 1kΩ
12V
HF
ADC
ADC
VS3
12 BITS
ADC
11012-013
Figure 17. Voltage Sense Configuration
ADCs
Two kinds of Σ-Δ ADCs are used in the feedback loop of the
ADP1046A: a low frequency (LF) ADC that runs at 1.56 MHz
and a high frequency (HF) ADC that runs at 25 MHz.
Σ-Δ ADCs have a resolution of one bit and operate differently
from traditional flash ADCs. The equivalent resolution that can
be obtained depends on how long the output bit stream of the
Σ-Δ ADC is sampled.
Σ-Δ ADCs also differ from Nyquist rate ADCs in that the quan-
tization noise is not uniform across the frequency spectrum. At
lower frequencies, the noise is lower, and at higher frequencies,
the noise is higher (see Figure 18).
MAGNITUDE
FREQUENCY
NYQUIST ADC
NOISE
Σ-Δ ADC
NOISE
11012-014
Figure 18. Noise Performance for Nyquist Rate and Σ-Δ ADCs
The low frequency ADC runs at approximately 1.56 MHz. For a
specified bandwidth, the equivalent resolution can be calculated
as follows:
ln(1.56 MHz/BW)/ln(2) = N bits
For example, at a bandwidth of 95 Hz, the equivalent
resolution/noise is
ln(1.56 MHz/95)/ln(2) = 14 bits
At a bandwidth of 1.5 kHz, the equivalent resolution/noise is
ln(1.56 MHz/1.5 kHz)/ln(2) = 10 bits
The high frequency ADC has a clock of 25 MHz. It is comb
filtered and outputs at the switching frequency (f
SW
) into the
digital filter. The equivalent resolution at some sample
frequencies is listed in Table 5.
Table 5. Equivalent Resolutions for High Frequency ADC
at Various Switching Frequencies
f
SW
(kHz) High Frequency ADC Resolution
48.8 9 bits
97.7 8 bits
195.3 7 bits
390.6 6 bits
The HF ADC has a range of ±30 mV. Using a base switching
frequency (f
SW
) of 100 kHz (8-bit HF ADC resolution), when f
SW
increases to 200 kHz (7-bit HF ADC resolution), the quantization
noise is 0.9375 mV (1 LSB). Increasing f
SW
to 400 kHz increases the
quantization noise to 3.75 mV (1 LSB = 2 × 30 mV/2
6
= 0.9375 mV).
VS1 OPERATION (VS1)
VS1 is used for the monitoring and protection of the power supply
voltage at the output of the LC stage, upstream of the OrFET. The
VS1 sense point on the power rail needs an external resistor
divider to bring the nominal input voltage to 1 V at the VS1 pin
(see Figure 17). The resistor divider is necessary because the VS1
ADC input range is 0 V to 1.6 V (12-bit reading). This divided-
down signal is internally fed into a low speed Σ-Δ ADC. The output
of the VS1 ADC goes to the digital filter and is also updated in
Register 0x15 every 10 ms. The VS1 signal is referenced to PGND.
When the OrFET is turned off, the power supply is regulated
from the VS1 sense point instead of the VS3± sense point.