Datasheet

Data Sheet ADP1046A
Rev. 0 | Page 11 of 88
Pin No. Mnemonic Description
14 OUTD PWM Output for Primary Side Switch. This signal is referenced to AGND. This pin can be disabled when not in use.
15 OUTAUX Auxiliary PWM Output. This signal is referenced to AGND. This pin can be disabled when not in use.
16 GATE OrFET Gate Drive Output. This signal is referenced to AGND. If this pin is not used, leave it floating.
17 SCL I
2
C Serial Clock Input. This signal is referenced to AGND.
18
SDA
I
2
C Serial Data Input and Output (Open Drain). This signal is referenced to AGND.
19 PSON Power Supply On Input. This signal is referenced to AGND. This pin is the hardware PSON control signal. It is
recommended that a 1 nF capacitor be connected from the PSON pin to AGND for noise debouncing and
decoupling.
20 FLAGIN Flag Input. An external signal can be input at this pin to generate a flag condition.
21 PGOOD2 Power-Good Output (Open Drain). This signal is referenced to AGND. This pin is controlled by the PGOOD2 flag.
This pin is set by a programmable combination of internal flags. If this pin is not used, connect it to AGND.
22 PGOOD1 Power-Good Output (Open Drain). This signal is referenced to AGND. This pin is controlled by the PGOOD1 flag.
This pin is set by a programmable combination of internal flags. If this pin is not used, connect it to AGND.
23 SHAREo Share Bus Output Voltage Pin. Connect this pin to 3.3 V through a pull-up resistor (typically 2.2 kΩ). When
configured for a digital share bus, this pin is a digital output. This signal is referenced to AGND. If this pin is
not used, connect it to AGND.
24 SHAREi Share Bus Feedback Pin. Connect this pin to the SHAREo pin. This signal is referenced to AGND. If this pin is not
used, connect it to AGND.
25 DGND Digital Ground. This pin is the ground reference for the digital circuitry of the ADP1046A. Star connect to AGND.
26 VCORE Output of the 2.5 V Regulator. Connect a decoupling capacitor of at least 330 nF (1 µF maximum) from this pin
to DGND as close to the IC as possible to minimize PCB trace length. It is recommended that the VCORE pin not
be used as a reference or to generate other logic levels using resistive dividers.
27 VDD Positive Supply Input. This signal is referenced to AGND. Connect a 4.7 µF decoupling capacitor from this pin to
AGND as close to the IC as possible to minimize PCB trace length.
28 RTD Thermistor Input. Place a thermistor (100 kΩ, 1%; beta = 4250, 1%) in parallel with a 16.5 kΩ, 1% resistor. This
pin is referenced to AGND. If this pin is not used, connect it to AGND.
29 ADD Address Select Input. This pin is used to program the I
2
C address. Connect a resistor from ADD to AGND. This
signal is referenced to AGND.
30 RES Resistor Input. This pin sets up the internal voltage reference for the ADP1046A. Connect a 10 kΩ, ±0.1% resistor
from RES to AGND. This signal is referenced to AGND.
31 VS3− Inverting Remote Voltage Sense Input. There should be a low ohmic connection to AGND. The resistor divider
on this input must have a tolerance specification of 0.5% or better to allow for trimming. Connect a 0.1 µF
capacitor from VS3− to AGND.
32 VS3+ Noninverting Remote Voltage Sense Input. This signal is referenced to VS3−, and the nominal input voltage at
this pin is 1 V. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for
trimming. This pin is the input to the high frequency Δ-Σ ADC.
EP Exposed Pad. The ADP1046A has an exposed thermal pad on the underside of the package. For increased
reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered
to the PCB AGND plane.