Data Sheet Digital Controller for Isolated Power Supply Applications ADP1046A FEATURES GENERAL DESCRIPTION Integrates all typical PWM controller functions 7 PWM control signals Digital control loop Integrated programmable loop filters Programmable voltage line feedforward Dedicated soft start filter Remote and local voltage sense Primary and secondary side current sense Synchronous rectifier control Current sharing OrFET control I2C interface Extensive fault detection and protection Extensive programmin
ADP1046A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 First Flag Fault ID and Value Registers ................................... 28 Applications ....................................................................................... 1 External Flag Input (FLAGIN Pin) .......................................... 28 General Description .........................................................................
Data Sheet ADP1046A Fault Conditions ..........................................................................39 ID Registers.................................................................................. 62 Timeout Condition .....................................................................39 PWM and Synchronous Rectifier Timing Registers .............. 63 Data Transmission Faults ...........................................................39 Digital Filter Programming Registers ..............
ADP1046A Data Sheet SPECIFICATIONS VDD = 3.0 V to 3.6 V, TA = −40°C to +125°C, unless otherwise noted. FSR = full-scale range. Table 1. Parameter SUPPLY Supply Voltage Supply Current Symbol Test Conditions/Comments Min Typ Max Unit VDD IDD 4.7 µF capacitor connected to AGND Normal operation (PSON is high or low) During EEPROM programming (40 ms) Shutdown (VDD below UVLO) 3.0 3.3 20 IDD + 8 100 3.6 V mA mA µA 2.75 3.0 2.97 4.
Data Sheet Parameter VS3 HIGH SPEED ADC Equivalent Sampling Frequency Equivalent Resolution Dynamic Range VS1 FAST OVP COMPARATOR Threshold Accuracy ADP1046A Symbol fSW = 390.6 kHz At factory trim of 1.2 V At other thresholds (0.8 V to 1.6 V) Does not include debounce time (Register 0x0A[7] = 1) VS1 UVP DIGITAL COMPARATOR VS1 UVP Accuracy Propagation Delay 6 ±30 Bits mV Equivalent resolution is 11 bits VIN % % ns +2.0 % FSR µs 0.5 V ns 80 0 0 Factory trimmed at 1.
ADP1046A Parameter CURRENT SENSE 2 (CS2+, CS2− PINS) Input Voltage Range Usable Input Voltage Range ADC Clock Frequency Temperature Coefficient 120 mV Range 60 mV Range Current Sense Measurement 120 mV Setting 60 mV Setting Current Sense Measurement Accuracy 120 mV Setting 60 mV Setting Current Sense Measurement Resolution CS2 Accurate OCP Speed Current Sink (High Side) Current Source (Low Side) Common-Mode Voltage at the CS2+ and CS2− Pins OrFET PROTECTION (CS2+, CS2−) Fast OrFET Accuracy Fast OrFET Speed
Data Sheet Parameter Measurement Accuracy ADP1046A Symbol Test Conditions/Comments Factory trimmed at 1 V 10 mV to 160 mV 0% to 100% of usable input voltage range Temperature Readings Using Internal Linearization Scheme T = 85°C with 100 kΩ||16.5 kΩ T = 100°C with 100 kΩ||16.
ADP1046A Data Sheet Parameter EEPROM RELIABILITY Endurance 1 Symbol Data Retention 2 1 2 Test Conditions/Comments Min TJ = 85°C TJ = 125°C TJ = 85°C TJ = 125°C 10,000 1000 20 10 Typ Max Unit Cycles Cycles Years Years Endurance is qualified as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, +85°C, and +125°C. Endurance conditions are subject to change pending EEPROM qualification.
Data Sheet ADP1046A ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2.
ADP1046A Data Sheet 32 31 30 29 28 27 26 25 VS3+ VS3– RES ADD RTD VDD VCORE DGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADP1046A TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 SHAREi SHAREo PGOOD1 PGOOD2 FLAGIN PSON SDA SCL NOTES 1. THE ADP1046A HAS AN EXPOSED THERMAL PAD ON THE UNDERSIDE OF THE PACKAGE. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE PCB AGND PLANE.
Data Sheet Pin No. 14 15 16 17 18 19 Mnemonic OUTD OUTAUX GATE SCL SDA PSON 20 21 FLAGIN PGOOD2 22 PGOOD1 23 SHAREo 24 SHAREi 25 26 DGND VCORE 27 VDD 28 RTD 29 ADD 30 RES 31 VS3− 32 VS3+ EP ADP1046A Description PWM Output for Primary Side Switch. This signal is referenced to AGND. This pin can be disabled when not in use. Auxiliary PWM Output. This signal is referenced to AGND. This pin can be disabled when not in use. OrFET Gate Drive Output. This signal is referenced to AGND.
ADP1046A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.5 4 MAX SPEC MAX SPEC 3 1.5 CS1 ADC ACCURACY (%FSR) MAX 1.0 0.5 MEAN 0 –0.5 MIN –1.0 –1.5 2 1 MAX 0 MIN –1 MEAN –2 –3 –2.0 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) –4 –60 11012-400 Figure 4. VS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR) –40 –20 0 100 120 140 2.0 1.5 CS2 ADC ACCURACY (%FSR) VS2 ADC ACCURACY (%FSR) 80 MAX SPEC 2.0 MAX 1.0 0.5 MEAN 0 –0.5 MIN –1.0 –1.5 1.5 MAX 1.0 0.
Data Sheet ADP1046A 1.28 2.5 MAX SPEC VS1 FAST OCP THRESHOLD (V) 1.5 MAX 1.0 0.5 MEAN 0 –0.5 MIN –1.0 –1.5 1.24 MAX 1.22 MEAN 1.20 MIN 1.18 1.16 1.14 MIN SPEC MIN SPEC –2.5 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 10. ACSNS ADC Accuracy vs. Temperature (from 10% to 90% of FSR) 1.220 MAX SPEC 1.215 MAX 1.210 1.205 MEAN 1.200 1.195 1.190 MIN 1.185 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 140 11012-405 MIN SPEC 1.180 –60 Figure 11.
ADP1046A Data Sheet THEORY OF OPERATION The ADP1046A is a secondary side controller for switch mode power supplies. It is designed for use in isolated redundant applications. The ADP1046A integrates the typical functions that are needed to control a power supply, such as The PWM block generates up to seven programmable PWM outputs for control of FET drivers and synchronous rectification FET drivers. This programmability allows many traditional and unique switching topologies to be realized.
Data Sheet ADP1046A CURRENT SENSE When using low-side current sensing, the current sources are 200 µA; therefore, the required resistor value is 1 V/200 µA = 5 kΩ. When using high-side current sensing, the current sources are 2 mA; therefore, the resistor value required is (VOUT − 1 V)/2 mA. In the case of VOUT = 12 V, the required resistor value is 5.5 kΩ. The ADP1046A has two current sense inputs: CS1 and CS2±.
ADP1046A Data Sheet For voltage monitoring, the VS1, VS2, and VS3 voltage value registers (Register 0x15, Register 0x16, and Register 0x17, respectively) are updated every 10 ms. The ADP1046A stores every ADC sample for 10 ms and then outputs the average value at the end of the 10 ms period. Therefore, if these registers are read at least every 10 ms, a true average value is read. The ADP1046A uses two separate sensing points: VS1 and VS3±, depending on the condition of the OrFET.
Data Sheet ADP1046A VS2 OPERATION (VS2) The feedforward scheme modifies the modulation value based on the ACSNS voltage. When the ACSNS input is 1 V, the line feedforward has no effect. For example, if the digital filter output remains unchanged and the ACSNS voltage changes to 50% of its original value (still higher than 0.5 V), the modulation of the falling edge of OUTx doubles and vice versa (see Figure 20). The voltage line feedforward function is optional and is programmable using Register 0x75.
ADP1046A Data Sheet To transfer the z-domain value to the s-domain, plug the following bilinear transformation equation into the H(z) equation: 2 f SW + s 2 f SW − s The digital filter introduces an extra phase delay element into the control loop. The digital filter circuit sends the duty cycle information to the PWM circuit at the beginning of each switching cycle (unlike an analog controller, which makes decisions on the duty cycle information continuously).
Data Sheet ADP1046A SYNCHRONOUS RECTIFICATION LIGHT LOAD MODE SR1 and SR2 are recommended for use as the PWM control signals when using synchronous rectification. These PWM signals can be configured much like the other PWM outputs. The ADP1046A can be configured to disable PWM outputs under light load conditions based on the value of CS2. Register 0x3B and Register 0x7D are used to program the light load mode thresholds for turn-off and turn-on of SR1, SR2, and other PWM outputs.
ADP1046A Data Sheet SOFT START The UVP fault is blanked only for the debounce time during soft start. Therefore, if the soft start period exceeds the debounce time, the UVP fault is triggered and stored in the first flag ID register (Register 0x10). A read of the latched fault registers and the first flag ID register clears the falsely triggered UVP condition.
Data Sheet ADP1046A t0 PS_ON DELAY (REG 0x2C[4:3]) RAMP TIME (REG 0x5F[7:5]) PGOOD DEBOUNCE (REG 0x2D) PSON VS3 UVP VS1 (VS1 – VS2) VOLTAGE OrFET ENABLE OrFET GATE LOOP CONTROLLED FROM VS1 LOOP CONTROLLED FROM VS3 UVP FLAG 11012-120 PGOOD1 Figure 24. Soft Start Timing Diagram RAMP TIME (REG 0x5F[7:5]) PSON 12.
ADP1046A Data Sheet OrFET CONTROL (GATE PIN) • The GATE control signal drives an external OrFET. The OrFET is used in redundant systems to protect against power flow into the power supply from the output terminals of another supply. This ensures that power flows only out of the power supply and that the unit can be hot-swapped. • The GATE pin is a totem-pole output and does not require a pull-up resistor. The GATE pin polarity can be programmed via Register 0x2D[1] to be active high or active low.
Data Sheet ADP1046A Short Circuit OrFET Operation Examples Hot Plug into a Live Bus A new PSU is plugged into a live 12 V bus (yellow). The internal voltage, VS1 (red), is ramped up before the OrFET is turned on. After the OrFET is turned on (green), current in the new PSU begins to flow to the load (blue). The turn-on voltage threshold between the new PSU and the bus is programmable. VS3 VS1 When one of the output rectifiers fails, the bus voltage can collapse if the OrFET is not promptly turned off.
ADP1046A Data Sheet VDD When VDD is applied, a certain time elapses before the part is capable of regulating the power supply. When VDD rises above the power-on reset and UVLO levels, it takes approximately 20 μs for VCORE to reach its operational point of 2.5 V. The EEPROM contents are then downloaded to the registers. The download takes an additional 25 μs (approximately). After the EEPROM download, the ADP1046A is ready for operation.
Data Sheet ADP1046A CURRENT SHARING During the next cycle, the slave increases its current output contribution by increasing its output voltage. This cycle continues until the slave outputs the same current as the master, within a programmable tolerance range. Figure 32 shows the configuration of the digital share bus. The ADP1046A supports both analog current sharing and digital current sharing.
ADP1046A Data Sheet Round 1 Figure 35 shows the possible signals on the share bus. In Round 1, every supply first places its MSB on the bus. If a supply senses that its MSB is the same as the value on the bus, it continues to Round 2. If a supply senses that its MSB is less than the value on the bus, it means that this supply must be a slave. LOGIC 1 LOGIC 0 t0 11012-025 t1 NEXT BIT tBIT If two units have the same MSB, they both continue to Round 2 because either of them may be the master.
Data Sheet ADP1046A POWER SUPPLY SYSTEM AND FAULT MONITORING The ADP1046A has extensive system and fault monitoring capabilities. The system monitoring functions include voltage, current, power, and temperature readings. The fault conditions include out-of-limit values for current, voltage, power, and temperature. The limits for the fault conditions are programmable. The ADP1046A has an extensive set of flags that are set when certain programmed thresholds or limits are exceeded.
ADP1046A Data Sheet The output of the RTD ADC is linearly proportional to the voltage on the RTD pin. However, thermistors exhibit a nonlinear function of resistance vs. temperature. Therefore, the user must perform postprocessing on the RTD ADC reading to accurately read the temperature. POWER READINGS The output power value register (Register 0x19) is the product of the VS3 voltage value and the CS2 current value.
Data Sheet ADP1046A Temperature Linearization Scheme OVERCURRENT PROTECTION (OCP) The ADP1046A implements a linearization scheme based on a preselected combination of thermistor (100 kΩ, 1%), external resistor (16.5 kΩ, 1%), and the 46 µA current source for best performance when linearizing measured temperatures in the industrial range. The ADP1046A has several OCP functions. CS1 and CS2± have separate OCP circuits to provide both primary and secondary side protection.
ADP1046A Data Sheet 5kΩ 5kΩ CS2+ ADC 1V 200µA 12 ASYNCHRONOUS 2.62ms AVERAGING PROGRAMMABLE DEBOUNCE AND ACTION (REG 0x0E AND REG 0x09) CS2 ACCURATE OCP SETTING REG 0x26 200µA 11012-136 CS2– Figure 40. CS2 OCP Detailed Internal Schematic CS2 OCP The constant current control loop is relatively low bandwidth because the current is averaged over a 328 µs period. The output voltage changes at a maximum rate of 1.
Data Sheet ADP1046A UNDERVOLTAGE PROTECTION (UVP) If the voltage sensed at the VS1 pin falls below the programmable UVP threshold, the UVP flag is set. The UVP threshold is programmed in Register 0x34; the GUI can also be used, as shown in Figure 42. The response to the UVP flag is programmable in Register 0x0B[3:0]. Undervoltage protection and the UVP flag are disabled during soft start. The equation to calculate the ADC code is given by the following formula: ADC Code = Vx/1.
ADP1046A Data Sheet The circuit monitors the current flowing in both legs of the fullbridge topology and stores this information. It compensates the selected PWM signals to ensure equal current flow in both legs of the full-bridge topology. The input is through the CS1 pin. Several switching cycles are required for the circuit to operate effectively. The maximum amount of modulation applied to each edge of the selected PWM outputs is programmable to ±80 ns or ±160 ns in Register 0x28[2].
Data Sheet ADP1046A POWER SUPPLY CALIBRATION AND TRIM The ADP1046A allows the entire power supply to be calibrated and trimmed digitally in the production environment. It can calibrate items such as output voltage and trim for tolerance errors introduced by sense resistors and resistor dividers, as well as its own internal circuitry. The part is factory trimmed, but it can be retrimmed by the user to compensate for the errors introduced by external components.
ADP1046A Data Sheet VOLTAGE CALIBRATION AND TRIM Trimming the Current Source The voltage sense inputs are optimized for sensing signals at 1 V (the usable input range is 1.4 V). In a 12 V system, a 12:1 resistor divider is required to reduce the 12 V signal to below 1.4 V. It is recommended that the output voltage of the power supply be reduced to 1 V at this pin for best performance. The tolerance of the resistor divider introduces errors that need to be trimmed.
Data Sheet ADP1046A Using the OTP Value The ADC is now trimmed and is linear between the two temperatures of interest. The second option does not use the linearization scheme. Instead, the user programs an RTD current and sets the OTP threshold in millivolts. Due to the nonlinear nature of the NTC thermistor, it is best to use a resistor in parallel with the NTC thermistor to aid in the linearization of the voltage seen at the RTD pin.
ADP1046A Data Sheet LAYOUT GUIDELINES This section explains best practices that should be followed to ensure optimal performance of the ADP1046A. In general, place all components as close to the ADP1046A as possible. All signals should be referenced to their respective grounds. CS1 CS2+ AND CS2− EXPOSED PAD Route the traces from the sense resistor to the ADP1046A parallel to each other. Keep the traces close together and as far from the switch nodes as possible.
Data Sheet ADP1046A I2C INTERFACE COMMUNICATION The ADP1046A I2C slave is a 2-wire interface that can be used to communicate with other I2C-compliant master devices and is compatible in a multimaster, multislave bus configuration. The function of the I2C slave is to decode the command sent from the master device and respond as requested. Communication is established using a 2-wire interface with a clock line (SCL) and data line (SDA).
Data transfer using the I2C slave is established using commands. All commands start with a slave address with the R/W bit cleared (set to 0), followed by the command code (register address). All commands supported by the ADP1046A follow one of the protocol types shown in Figure 47 to Figure 53.
Data Sheet ADP1046A GENERAL CALL SUPPORT DATA TRANSMISSION FAULTS The ADP1046A is capable of decoding and acknowledging a general call address. The general call address is supported for send, write, and read commands that use Address 0x00 as the slave address. The I2C slave responds to both its own address and to the general call address (0x00). Data transmission faults occur when two communicating devices violate the I2C communication protocol.
ADP1046A Data Sheet Invalid or Unsupported Command Code Write to Read-Only Commands If an invalid or unsupported command code is sent to the I2C slave, the I2C slave considers this a data content fault and responds as follows: If a host performs a write to a read-only command, the I2C slave considers this a data content fault and responds as follows: • • • Issues a no acknowledge for the illegal/unsupported command byte and data bytes Flushes and ignores the received command and data • Issues a no
Data Sheet ADP1046A EEPROM The EEPROM controller provides an interface between the ADP1046A core logic and the built-in Flash/EE. The user can control data access to and from the EEPROM through this controller interface. Different I2C commands are available for the different operations to the EEPROM. Communication is initiated by the master device sending a command to the I2C slave device to access data from or send data to the EEPROM.
ADP1046A Data Sheet WRITE OPERATION (BYTE WRITE AND BLOCK WRITE) EEPROM PASSWORD Write to Main Block, Page 0 and Page 1 Page 0 and Page 1 of the main block are reserved for storing the default settings and user settings, respectively. The user cannot perform a direct write operation to Page 0 or Page 1 using the EEPROM_DATA_00 and EEPROM_DATA_01 commands. A user write to Page 0 or Page 1 returns a no acknowledge.
Data Sheet ADP1046A SAVING REGISTER SETTINGS TO THE EEPROM EEPROM CRC CHECKSUM The register settings cannot be saved to the factory default settings located in Page 0 of the EEPROM main block. This is to prevent the user from accidentally overriding the factory trim settings and default register settings. As a simple method of checking that the values downloaded from the EEPROM are consistent with the internal registers, a CRC checksum is implemented.
ADP1046A Data Sheet SOFTWARE GUI The GUI is also an information center, displaying the status of all readings, monitoring, and flags on the ADP1046A. For more information about the GUI, contact Analog Devices for the latest software and a user guide. Evaluation boards are also available by contacting Analog Devices. 11012-407 A free software GUI is available for programming and configuring the ADP1046A.
Data Sheet ADP1046A REGISTER LISTING Table 7.
ADP1046A Data Sheet Address Register Name Voltage Sense Registers 0x31 VS3 voltage setting (remote voltage) 0x32 VS1 overvoltage limit (OVP) 0x33 VS2 and VS3 overvoltage limit (OVP) 0x34 VS1 undervoltage limit (UVP) 0x35 Line impedance limit 0x36 Load line impedance 0x37 Fast OVP comparator 0x38 VS1 trim 0x39 VS2 trim 0x3A VS3 trim 0x3B Light load mode disable settings ID Registers 0x3C Silicon revision ID 0x3D Manufacturer ID 0x3E Device ID PWM and Synchronous Rectification Timing Registers 0x3F OUTAUX s
Data Sheet ADP1046A Address Register Name 0x65 Light load mode digital filter zero setting 0x66 Light load mode digital filter pole setting 0x67 Light load mode digital filter HF gain setting 0x68 Reserved Soft Start Filter Programming Registers 0x71 Soft start digital filter LF gain setting 0x72 Soft start digital filter zero setting 0x73 Soft start digital filter pole setting 0x74 Soft start digital filter HF gain setting Extended Functions Registers 0x75 Voltage line feedforward 0x76 Volt-second balanc
ADP1046A Data Sheet DETAILED REGISTER DESCRIPTIONS FAULT REGISTERS Register 0x04 to Register 0x07 are latched fault registers. In these registers, flags are not reset when the fault disappears. Flags are cleared only by a register read (provided that the fault no longer persists). Note that latched bits are clocked on a low-to-high transition only. Also note that these register bits are cleared when read via the I2C interface unless the fault is still present.
Data Sheet ADP1046A Table 10. Register 0x02—Fault Register 3 and Register 0x06—Latched Fault Register 3 (1 = Fault, 0 = Normal Operation) Bits 7 6 5 4 Bit Name OTP Fast OVP Share bus Constant current R/W R R R R 3 2 1 0 Soft start Line impedance Soft start filter External flag R R R R Description Temperature is above OTP limit. Fast OVP threshold was exceeded. Current share is outside regulation limit. Power supply is operating in constant current mode (constant current mode is enabled).
ADP1046A Data Sheet Register 0x08 to Register 0x0D allow the user to program the response when each flag is set. Table 13. Register 0x08 to Register 0x0D—Fault Configuration Register Bit Descriptions Bits 7 Bit Name Timing R/W R/W [6:4] Action R/W 3 [2:0] Timing Action R/W R/W Description This bit specifies when the flag is set. 0 = after debounce. 1 = immediately. These bits specify the action that the part takes in response to the flag.
Data Sheet ADP1046A Register 0x0F allows the user to program the ADP1046A to ignore the specified flags until the end of the soft start ramp time. The UVP and ACSNS flags are always active during soft start. Table 15.
ADP1046A Data Sheet Table 18. Register 0x12—HF ADC Reading Bits [7:0] Bit Name HF ADC reading R/W R Description This register contains the reading from the high frequency ADC. Table 19. Register 0x13—CS1 Value (Input Current) Bits [15:4] Bit Name Input current value R/W R [3:0] Reserved R Description This register contains the 12-bit input current information. This value is derived from a voltage measurement at the CS1 input.
Data Sheet ADP1046A Table 24. Register 0x18—CS2 Value (Output Current) Bits [15:4] Bit Name Output current value R/W R [3:0] Reserved R Description This register contains the 12-bit output current information. This value is the voltage drop across the sense resistor. To obtain the current value, the user must divide the value of this register by the sense resistor value (see the CS2+, CS2− Pins section). The CS2± pins have a full-scale input range of 120 mV or 60 mV (set in Register 0x27[5]).
ADP1046A Data Sheet CURRENT SENSE AND CURRENT LIMIT REGISTERS Table 33. Register 0x21—CS1 Gain Trim Bits 7 Bit Name Gain polarity R/W R/W [6:0] CS1 gain trim R/W Description 1 = negative gain is introduced. 0 = positive gain is introduced. This value calibrates the primary side current sense gain. See the CS1 Trim section for more information. Table 34.
Data Sheet ADP1046A Table 39. Register 0x27—CS1/CS2 Fast OCP Settings Bits [7:6] Bit Name CS1 fast OCP debounce R/W R/W 5 CS2 nominal voltage drop R/W 4 3 CS1 fast OCP bypass Constant current mode R/W R/W 2 CS2 current sensing R/W [1:0] CS1 fast OCP timeout R/W Description These bits set the CS1 fast OCP debounce value. This is the minimum time that the CS1 signal must be constantly above the fast OCP limit before the PWM outputs are shut down.
ADP1046A Data Sheet Table 41. Register 0x29—Share Bus Bandwidth Bits [7:5] 4 Bit Name Reserved Bit stream R/W R/W R/W 3 Current share enable Share bus bandwidth R/W [2:0] R/W Description Reserved. 1 = the current sense ADC reading is output on the SHAREo pin. This bit stream can be used for analog current sharing. 0 = the digital share bus signal is output on the SHAREo pin. This signal can be used for digital current sharing. 1 = Reserved. 0 = CS2 reading used for current share.
Data Sheet ADP1046A Bits 2 1 Bit Name Reserved Disable light load during soft start R/W R/W R/W 0 Force soft start filter R/W Description Set this bit to 0 for normal operation. 0 = allow switching to light load mode filter during soft start. 1 = never switch to light load mode filter during soft start. 0 = use normal mode filter or soft start filter, depending on the OrFET status. If regulating from VS3 (OrFET on), the normal mode filter is used.
ADP1046A Data Sheet Table 47. Register 0x2F—OTP Threshold Bits [7:0] Bit Name OTP threshold R/W R/W Description This register, adding 0 as the MSB, results in a 9-bit OTP threshold value. This 9-bit value is compared to the nine MSBs of the RTD ADC reading. If the RTD ADC reading is lower than the threshold set by these bits, the OTP flag is set. This 8-bit register provides 256 threshold settings from 0 mV to 800 mV. One LSB equates to 800 mV/256 = 3.125 mV.
Data Sheet ADP1046A VOLTAGE SENSE REGISTERS Table 49. Register 0x31—VS3 Voltage Setting (Remote Voltage) Bits [7:0] Bit Name VS3 voltage setting R/W R/W Description This register is used to set the output voltage (voltage differential at the VS3+ and VS3− pins). Each LSB corresponds to a 0.6% increase. Setting this register to a value of 0xA0 gives an output voltage setting of 100% of the nominal voltage.
ADP1046A Bits [1:0] Bit Name OVP sampling Data Sheet R/W R/W Description The OVP flag is set if the average voltage during the OVP sampling period is greater than the OVP threshold. This OVP flag sampling period is 80 μs. The number of samples can be increased using these bits. If the number of samples is increased, the average voltage must be greater than the OVP threshold for each of those cycles.
Data Sheet Bits [2:0] Bit Name Load line setting ADP1046A R/W R/W Description These bits specify how much the output voltage decreases from nominal at full load. The amount of output resistance introduced can be calculated as follows (these bits specify the value of N): ROUT = 0.1 × VOUT_NOM × CS2 RSENSE/(CS2 Range × 2N) For more information, see the Digital Load Line and Slew Rate section.
ADP1046A Data Sheet Table 59. Register 0x3B—Light Load Mode Disable Settings Bits 7 Bit Name Disable OUTAUX R/W R/W 6 Disable OUTD R/W 5 Disable OUTC R/W 4 Disable OUTB R/W 3 Disable OUTA R/W [2:0] Light load SR disable R/W Description Setting this bit means that OUTAUX is also disabled if the load current falls below the light load SR disable threshold. Setting this bit means that OUTD is also disabled if the load current falls below the light load SR disable threshold.
Data Sheet ADP1046A PWM AND SYNCHRONOUS RECTIFIER TIMING REGISTERS Figure 57 and Table 63 to Table 93 describe the implementation and programming of the seven PWM signals that are output from the ADP1046A. In general, it is recommended that t1 be set to 0 and that t1 be set as the reference point for the other signals.
ADP1046A Bits [5:0] Bit Name Switching frequency Data Sheet R/W R/W Description Bit 5 Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 3 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 Bit 2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 Rev.
Data Sheet ADP1046A Table 64. Register 0x40—PWM Switching Frequency Setting Bits [7:6] [5:0] Bit Name Reserved Switching frequency R/W R/W R/W Description Reserved. This register sets the switching frequency of all the PWM pins other than the OUTAUX pin. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Frequency (kHz) 0 0 0 0 0 0 48.83 0 0 0 0 0 1 50.40 0 0 0 0 1 0 52.08 0 0 0 0 1 1 53.88 0 0 0 1 0 0 55.80 0 0 0 1 0 1 57.87 0 0 0 1 1 0 60.1 0 0 0 1 1 1 62.5 0 0 1 0 0 0 65.1 0 0 1 0 0 1 67.93 0 0 1 0 1 0 71.
ADP1046A Bits [5:0] Bit Name Switching frequency Data Sheet R/W R/W Description Bit 5 Bit 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 3 0 0 0 0 0 0 1 Bit 2 0 0 0 1 1 1 1 Bit 1 0 1 1 0 0 1 1 Bit 0 1 0 1 0 1 0 1 Frequency (kHz) 416.67 446.43 480.77 520.83 568.18 625 Resonant mode Table 65. Register 0x41—OUTA Rising Edge Timing (OUTA Pin) Bits [7:0] Bit Name t1 R/W R/W Description This register contains the eight MSBs of the 12-bit t1 time.
Data Sheet ADP1046A Table 69. Register 0x45—OUTB Rising Edge Timing (OUTB Pin) Bits [7:0] Bit Name t3 R/W R/W Description This register contains the eight MSBs of the 12-bit t3 time. This value is always used with the top four bits of Register 0x46, which contains the four LSBs of the t3 time. Each LSB corresponds to 5 ns resolution. The entire switching period is divided into 40 ns time steps. If the tRx and tFx of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V.
ADP1046A Data Sheet Table 74. Register 0x4A—OUTC Rising Edge Setting (OUTC Pin) Bits [7:4] Bit Name t5 R/W R/W 3 Modulate enable R/W 2 t5 sign R/W 1 0 Reserved Volt-second balance source selection R/W R/W Description These bits contain the four LSBs of the 12-bit t5 time. This value is always used with the eight bits of Register 0x49, which contains the eight MSBs of the t5 time. Each LSB corresponds to 5 ns resolution. The entire switching period is divided into 40 ns time steps.
Data Sheet ADP1046A Table 78. Register 0x4E—OUTD Rising Edge Setting (OUTD Pin) Bits [7:4] Bit Name t7 R/W R/W 3 Modulate enable R/W 2 t7 sign R/W 1 0 Reserved Volt-second balance source selection R/W R/W Description These bits contain the four LSBs of the 12-bit t7 time. This value is always used with the eight bits of Register 0x4D, which contains the eight MSBs of the t7 time. Each LSB corresponds to 5 ns resolution. The entire switching period is divided into 40 ns time steps.
ADP1046A Data Sheet Table 82. Register 0x52—SR1 Rising Edge Setting (SR1 Pin) Bits [7:4] Bit Name t9 R/W R/W 3 Modulate enable R/W 2 t9 sign R/W 1 0 Reserved SR soft start edge control R/W R/W Description These bits contain the four LSBs of the 12-bit t9 time. This value is always used with the eight bits of Register 0x51, which contains the eight MSBs of the t9 time. Each LSB corresponds to 5 ns resolution. The entire switching period is divided into 40 ns time steps.
Data Sheet ADP1046A Table 86. Register 0x56—SR2 Rising Edge Setting (SR2 Pin) Bits [7:4] Bit Name t11 R/W R/W 3 Modulate enable R/W 2 t11 sign R/W [1:0] Reserved R/W Description These bits contain the four LSBs of the 12-bit t11 time. This value is always used with the eight bits of Register 0x55, which contains the eight MSBs of the t11 time. Each LSB corresponds to 5 ns resolution. The entire switching period is divided into 40 ns time steps.
ADP1046A Data Sheet Table 90. Register 0x5A—OUTAUX Rising Edge Setting (OUTAUX Pin) Bits [7:4] Bit Name t13 R/W R/W 3 Modulate enable R/W 2 t13 sign R/W [1:0] Reserved R/W Description These bits contain the four LSBs of the 12-bit t13 time. This value is always used with the eight bits of Register 0x59, which contains the eight MSBs of the t13 time. Each LSB corresponds to 5 ns resolution. The entire switching period is divided into 40 ns time steps.
Data Sheet ADP1046A Table 93. Register 0x5D—OUTx and SRx Pin Disable Settings Bits 7 6 5 4 3 2 1 0 Bit Name OUTAUX disable SR2 disable SR1 disable OUTD disable OUTC disable OUTB disable OUTA disable GATE disable R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit disables the OUTAUX output. Setting this bit disables the SR2 output. Setting this bit disables the SR1 output. Setting this bit disables the OUTD output. Setting this bit disables the OUTC output.
ADP1046A Bits [2:0] Bit Name Slew rate Data Sheet R/W R/W Description These bits specify the slew rate at the VS3± pins for the change in the voltage reference setting. Bit 2 Bit 1 Bit 0 Slew Rate 0 0 0 200 mV/ms 0 0 1 100 mV/ms 0 1 0 50 mV/ms 0 1 1 25 mV/ms 1 0 0 12.5 mV/ms 1 0 1 6.25 mV/ms 1 1 0 3.125 mV/ms 1 1 1 1.5625 mV/ms (4 LSB/ms) Table 96.
Data Sheet ADP1046A SOFT START FILTER PROGRAMMING REGISTERS Table 105. Register 0x71—Soft Start Digital Filter LF Gain Setting Bits [7:0] Bit Name LF gain setting R/W R/W Description This register determines the low frequency gain of the loop response during soft start. The LF gain is programmable over a 20 dB range (see Figure 58). Table 106.
ADP1046A Data Sheet Bits 2 Bit Name t3 sign R/W R/W 1 Modulate enable, t4 R/W 0 t4 sign R/W Description 0 = positive sign. Increase of balance control modulation moves t3 right. 1 = negative sign. Increase of balance control modulation moves t3 left. Setting this bit enables modulation from balance control on the OUTB falling edge, t4. It is recommended that volt-second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. 0 = positive sign.
Data Sheet ADP1046A Table 113. Register 0x79—SR Delay Compensation Bits [7:6] [5:0] Bit Name Reserved SR driver delay R/W R/W R/W Description Reserved. These bits specify the 6-bit representation of the SR delay in steps of 5 ns. 000000 = 0 ns. 111111 = 63 ns × 5 ns = 315 ns. Table 114. Register 0x7A—Filter Transitions Bits [7:6] [5:3] 2 Bit Name Reserved HF ADC configuration Enable soft transition R/W R/W R/W R/W [1:0] Transition speed R/W Description Reserved.
ADP1046A Data Sheet Table 117. Register 0x7D—Light Load Mode Threshold Settings Bits [7:6] [5:4] Bit Name Reserved Debounce R/W R/W R/W [3:2] Light load mode averaging speed R/W [1:0] Light load mode hysteresis R/W Description Reserved. After the SR outputs are turned on or off, any further transition of the thresholds is ignored for the amount of time programmed in these bits. This debounce is provided to avoid false transitions and improve noise immunity.
Data Sheet ADP1046A EEPROM REGISTERS Refer to the I2C communication protocol specification for more information about how to write these commands to the ADP1046A. Table 119. Register 0x81—RESTORE_DEFAULT_ALL Bits N/A Bit Name RESTORE_DEFAULT_ALL Type Send byte Description Download the factory default settings from EEPROM (Page 0 of the main block) into operating memory. The password is also reset to the default value (0xFF). Table 120.
ADP1046A Data Sheet Table 128. Register 0x8A—EEPROM_INFO Bits Variable Bit Name EEPROM_INFO Type Block read Description Block read from the EEPROM INFO block. Table 129. Register 0x8B—EEPROM_DATA_00 Bits Variable Bit Name EEPROM_DATA_00 Type Block read Description Block read from the EEPROM main block, Page 0. The EEPROM must first be unlocked. This page contains the factory default settings. Table 130.
Data Sheet ADP1046A Table 138. Register 0x94—EEPROM_DATA_09 Bits Variable Bit Name EEPROM_DATA_09 Type Block read/ write Description Block read or write from the EEPROM main block, Page 9. To write to this page, the EEPROM must first be unlocked. This page is available to the user for storing data. Table 139. Register 0x95—EEPROM_DATA_10 Bits Variable Bit Name EEPROM_DATA_10 Type Block read/ write Description Block read or write from the EEPROM main block, Page 10.
ADP1046A Data Sheet RESONANT MODE OPERATION SYNCHRONOUS RECTIFICATION IN RESONANT MODE The ADP1046A supports control of a resonant converter. Resonant converters are an alternative to traditional fixed frequency converters. They offer high switching frequency, small size, and high efficiency. Figure 59 illustrates a widely used series resonant converter. QC QA Control of the synchronous rectifiers in a resonant controller is a complicated issue.
Data Sheet ADP1046A ADJUSTING THE TIMING OF THE PWM OUTPUTS SOFT START IN RESONANT MODE To accurately adjust the timing of the PWM outputs, the following registers can be used to set the dead time and delays of the PWM outputs: Register 0x41, Register 0x43, Register 0x45, Register 0x47, Register 0x49, Register 0x4B, Register 0x4D, Register 0x4F, Register 0x51, Register 0x53, Register 0x55, and Register 0x57. The resolution for adjusting the dead time is 5 ns.
ADP1046A Data Sheet RESONANT MODE REGISTER DESCRIPTIONS Table 145. Register 0x40—PWM Switching Frequency Setting in Resonant Mode Bits [7:6] [5:0] Bit Name Reserved Switching frequency R/W R/W R/W Description Reserved. This register sets the switching frequency of the PWM pins and enables resonant mode. To enable resonant mode, set these bits to 0x3F (111111). Table 146.
Data Sheet ADP1046A Table 150. Register 0x45—OUTB Rising Edge Dead Time in Resonant Mode Bits [7:0] Bit Name Δt3 (rising edge dead time of OUTB) R/W R/W Description This register sets Δt3, which is the delay time of the rising edge of OUTB from the start of the switching cycle, tA. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Δt3 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 … … … … … … … … … 1 1 1 1 1 1 1 1 1275 Table 151.
ADP1046A Data Sheet Table 154. Register 0x49—OUTC Rising Edge Dead Time in Resonant Mode Bits [7:0] Bit Name Δt5 (rising edge dead time of OUTC) R/W R/W Description This register sets Δt5, which is the difference between the rising edge of OUTC and the midpoint of the switching cycle, tB. Each LSB corresponds to 5 ns of resolution. When the register value is from 0x00 to 0x7F, the rising edge of OUTC is trailing tB. When the value is from 0x80 to 0xFF, the rising edge of OUTC is leading tB.
Data Sheet ADP1046A Table 158. Register 0x4F—OUTD Falling Edge Dead Time in Resonant Mode Bits [7:0] Bit Name Δt8 (falling edge dead time of OUTD) R/W R/W Description This register sets Δt8, which is the leading time of the falling edge of OUTD from the end of the switching cycle, tC. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Δt8 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 … … … … … … … … … 1 1 1 1 1 1 1 1 1275 Table 159.
ADP1046A Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 63.
