Datasheet

Data Sheet ADN8831
Rev. A | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE LFCSP PACKAGE HAS AN EXPOSED PADDLE
THAT SHOULD BE CONNECTED TO AGND (PIN 12)
AND THE ASSOCIATED PCB GROUND PLANE.
PIN 1
INDICATOR
1ILIMC
2IN1P
3IN1N
4OUT1
5IN2P
6IN2N
7OUT2
8VREF
24 COMPSW
23 SFB
22 PGND
21 SNGATE
20 SW
19 SPGATE
18 PVDD
17 COMPOSC
9AVDD
10PHASE
11TMPGD
12AGND
13F
REQ
14SS/SB
15SYNCO
16SYNCI/SD
32
ILIMH
31
VLIM
30
VTEC
29
ITEC
28
CS
27
LFB
26
LNGATE
25
LPGATE
TOP VIEW
(Not to Scale)
ADN8831
04663-002
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Type Description
1
ILIMC
Analog Input
Sets TEC Cooling Current Limit.
2 IN1P Analog Input Noninverting Input to Error Amplifier.
3 IN1N Analog Input Inverting Input to Error Amplifier.
4 OUT1 Analog Output Output of Error Amplifier.
5 IN2P Analog Input Noninverting Input to Compensation Amplifier.
6 IN2N Analog Input Inverting Input to Compensation Amplifier.
7 OUT2 Analog Output Output of Compensation Amplifier.
8 VREF Analog Output 2.5 V Voltage Reference Output.
9 AVDD Power Power for Nondriver Sections. 3.0 V minimum; 5.5 V maximum.
10 PHASE Analog Input Sets SYNCO Clock Phase Relative to SYNCI/
SD
Clock.
11 TMPGD Digital Output Logic Output. Active high. Indicates when the OUT1 voltage is within ±100 mV of IN2P voltage.
12
AGND
Ground
Analog Ground. Connect to low noise ground.
13 FREQ Analog Input Sets Switching Frequency with an External Resistor.
14 SS/
SB
Analog Input Sets Soft Start Time for Output Voltage. Pull low (VTEC = 0 V) to put the ADN8831 into standby
mode.
15 SYNCO Digital Output Phase Adjustment Clock Output. Phase set from PHASE pin. Used to drive SYNCI/
SD
of other
ADN8831 devices.
16 SYNCI/
SD
Digital Input Optional Clock Input. If not connected, clock frequency is set by FREQ pin. Pull low to put
the ADN8831 into shutdown mode. Pull high to negate shutdown mode.
17 COMPOSC Analog Output Compensation for Oscillator. Connect to PVDD when in free-run mode, connect to R-C
network when in external clock mode.
18 PVDD Power Power for Output Driver Sections. 3.0 V minimum; 5.5 V maximum.
19 SPGATE Analog Output PWM Output Drives External PMOS Gate.
20 SW Analog Input Connects to PWM FET Drains.
21 SNGATE Analog Output PWM Output Drives External NMOS Gate.
22 PGND Ground Power Ground. External NMOS devices connect to PGND. Connect to digital ground.
23 SFB Analog Input PWM Feedback. Connect to the TEC module negative (−) terminal.
24 COMPSW Analog Input Compensation Pin for Switching Amplifier.
25
LPGATE
Analog Output
Linear Output Drives External PMOS Gate.
26 LNGATE Analog Output Linear Output Drives External NMOS Gate.
27 LFB Analog Input Linear Feedback. Connect to H-Bridge transistor output and current sense resistor.
28 CS Analog Input Linear Feedback. Connect to the TEC module positive (+) terminal.
29 ITEC Analog Output Indicates TEC Current.