Datasheet

REV. –2–
ADN8830–SPECIFICATIONS
(@ V
DD
= 3.3 V to 5.0 V, V
GND
= 0 V, T
A
= 25ⴗC, T
SET
= 25ⴗC, using typical application
configuration as shown in Figure 1, unless otherwise noted.)
Parameter Symbol Conditions Min Typ Max Unit
TEMPERATURE STABILITY
Long-Term Stability Using 10 kΩ thermistor with
 = –4.4% at 25°C 0.01 °C
PWM OUTPUT DRIVERS
Output Transition Time t
R
, t
F
C
L
= 3,300 pF 20 ns
Nonoverlapping Clock Delay 50 65 ns
Output Resistance R
O
(N1, P1) I
L
= 50 mA 6 Ω
Output Voltage Swing OUT A V
LIM
= 0 V 0 V
DD
V
Output Voltage Ripple OUT A f
CLK
= 1 MHz 0.2 %
Output Current Ripple I
TEC
f
CLK
= 1 MHz 0.2 %
LINEAR OUTPUT AMPLIFIER
Output Resistance R
O, P2
I
OUT
= 2 mA 85 Ω
R
O, N2
I
OUT
= 2 mA 178 Ω
Output Voltage Swing OUT B 0 V
DD
V
POWER SUPPLY
Power Supply Voltage V
DD
3.0 5.5 V
Power Supply Rejection Ratio PSRR V
DD
= 3.3 V to 5 V, V
TEC
= 0 V 80 92 dB
–40°C ≤ T
A
≤ +85°C60 dB
Supply Current I
SY
PWM not switching 8 12 mA
–40°C ≤ T
A
≤ +85°C15mA
Shutdown Current I
SD
Pin 10 = 0 V 5 μA
Soft-Start Charging Current I
SS
15 μA
Undervoltage Lockout V
OLOCK
Low-to-high threshold 2.0 2.7 V
ERROR AMPLIFIER
Input Offset Voltage V
OS
V
CM
= 1.5 V 50 250 μV
Gain A
V, IN
20 V/V
Input Voltage Range V
CM
0.2 2.0 V
Common-Mode Rejection Ratio CMRR 0.2 V < V
CM
< 2.0 V 58 68 dB
–40°C ≤ T
A
≤ +85°C55 dB
Open-Loop Input Impedance R
IN
1GΩ
Gain-Bandwidth Product GBW 2 MHz
REFERENCE VOLTAGE
Reference Voltage V
REF
I
REF
< 2 mA 2.37 2.47 2.57 V
OSCILLATOR
Synchronization Range f
CLK
Pin 25 connected to external clock 200 1,000 kHz
Oscillator Frequency f
CLK
Pin 24 = V
DD
; (R = 150 kΩ; 800 1,000 1,250 kHz
Pin 25 = GND)
LOGIC CONTROL*
Logic Low Input Threshold 0.2 V
Logic High Input Threshold 3 V
Logic Low Output Level 0.2 V
Logic High Output Threshold V
DD
– 0.2 V
*Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 μA).
Specifications subject to change without notice.
D