Datasheet

REV.
ADN8830
–17–
Although the FETs that drive OUT A alternate between Q1 and
Q2 being on, they have an equivalent series resistance that is
equal to a weighted average of their r
DS, ON
values.
RDr Dr
EQIV DS P DS N
=× +
()
×
,,
–
11
1
(35)
The resistive power loss from the PWM transistors is then
PRI
FET PWM EQIV TEC,
=×
2
(36)
There is also a power loss from the continuing charging and
discharging of the gate capacitances on Q1 and Q2. The power
dissipated due to gate charge loss (P
GCL
) is
PCVf
GCL ISS DD CLK
=
1
2
2
(37)
using the appropriate input capacitance (C
ISS
) for the NMOS
and PMOS. Both transistors are switching, so P
GCL
should be
calculated for each one and will be added to find the total power
dissipated from the circuit.
The series resistance of the inductor, R2 from Figure 14, will
also exhibit a power dissipation equal to
PRI
R TEC2
2
2=×
(38)
Core loss from the inductor arises as a result of nonidealities of
the inductor. Although this is difficult to calculate explicitly, it
can be estimated as 80% of P
RLS
at 1 MHz switching frequen-
cies and 50% of P
RL
at 100 kHz. Judging conservatively
PP
LOSS RL
=×08.
(39)
Finally, the power dissipated by the ADN8830 is equal to the
current used by the device multiplied by the supply voltage.
Again, this exact equation is difficult to determine as we have
already taken into account some of the current while finding the
gate charge loss. A reasonable estimate is to use 40 mA as the
total current used by the ADN8830. The power dissipated from
the device itself is
PVmA
ADN DD8830
10=×
(40)
There are certainly other minor mechanisms for power dissipa-
tion in the circuit. However, a rough estimate of the total power
dissipated can be found by summing the preceding power dissi-
pation equations. Efficiency is then found by comparing the
power dissipated with the required output power to the load.
Efficiency
P
PP
LOAD
LOAD DISS TOT
=
+
,
(41)
where
PIV
LOAD LOAD LOAD
=×
The measured efficiency of the system will likely be less than the
calculated efficiency. Measuring the efficiency of the application
circuit is fairly simple but must be done in an exact manner to
ensure the correct numbers are being measured. Using two high
current, low impedance ammeters and two voltmeters, the cir-
cuit should be set up as shown in Figure 15.
A
V
DD
POWER SUPPLY
GND
ADN8830
V
V
A
TEC
LOAD
Figure 15. Measuring Efficiency of the ADN8830 Circuit
Table V. Recommended FETs for Linear Output Amplifier
Part Number Type C
GD
(nF) Ext. C
GD
(nF) C
SNUB
(nF) r
DS, ON
(m⍀)I
MAX
(A) Manufacturer
FDW2520C* NMOS 0.17 18 6.0 Fairchild
PMOS 0.15 2.2 3.3 35 4.5 Fairchild
IRF7401 NMOS 0.5 22 8.7 International Rectifier
IRF7233 PMOS 2.2 1.0 3.3 20 9.5 International Rectifier
FDR6674A NMOS 0.23 9.5 11.5 Fairchild
FDR840P PMOS 0.6 1.0 3.3 12 10 Fairchild
*Recommend transistors in typical application circuit Figure 1.
Table VI. Recommended FETs for PWM Output Amplifier
Part Number Type C
ISS
(nF) r
DS,ON
(m⍀) Continuous I
MAX
(A) Manufacturer
FDW2520C* NMOS 1.33 18 6.0 Fairchild
PMOS 1.33 35 4.5 Fairchild
Si7904DN NMOS 1.0 30 5.3 Vishay Siliconix
Si7401DN PMOS 3.5 17 7.3 Vishay Siliconix
IRF7401 NMOS 1.6 22 8.7 International Rectifier
IRF7404 PMOS 1.5 40 6.7 International Rectifier
*Recommend transistors in typical application circuit Figure 1.
D