Datasheet

ADN8810
Rev. A | Page 5 of 16
TIMING CHARACTERISTICS
1, 2
Table 2. Timing Characteristics
Parameter Description Min Typ Max Unit
f
CLK
SCLK Frequency 12.5 MHz
t
1
SCLK Cycle Time 80 ns
t
2
SCLK Width High 40 ns
t
3
SCLK Width Low 40 ns
t
4
CS
15
Low to SCLK High Setup
ns
t
5
CS
15
High to SCLK High Setup
ns
t
6
SCLK High to
CS
35
Low Hold
ns
t
7
SCLK High to
CS
20
High Hold
ns
t
8
Data Setup 15 ns
t
9
Data Hold 2 ns
t
10
CS
30
High Pulsewidth
ns
t
11
RESET
40
Pulsewidth
ns
t
12
CS
High to
30
RESET
Low Hold
ns
NOTES
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10%
to 90% of DVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
SCLK
CS
SDI
t
6
t
4
t
3
t
2
t
7
t
5
t
1
t
10
t
8
t
9
A3*
A2
t
12
t
11
A1 A0 D11 D10 D0
RESET
*ADDRESS BIT A3 MUST BE LOGIC LOW
03195-0-002
Figure 2. Timing Diagram