Datasheet

ADN8102
Rev. B | Page 7 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
0
7060-002
NOTES
1. EXPOSED PAD MUST BE CONNECTED TO VEE.
PIN 1
INDICATOR
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VEE
LB
ON_B0
OP_B0
VCC
ON_B1
OP_B1
VTTO
ON_B2
OP_B2
VEE
ON_B3
OP_B3
ENB
PE_B1 PE_B0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PE_A1 PE_A0 ENA OP_A0 ON_A0 VCC OP_A1 ON_A1 VTTO OP_A2 ON_A2 VEE OP_A3 ON_A3 ADDR1 ADDR0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RESET
LOS_
A
IN_A0
IP_A0
VCC
IN_A1
IP_A1
VTTI
IN_A2
IP_A2
VEE
IN_A3
IP_A3
DVCC
EQ_A1
EQ_A0
SCL
SDA
LOS_B
IP_B0
IN_B0
VCC
IP_B1
IN_B1
VTTI
IP_B2
IN_B2
VEE
IP_B3
IN_B3
EQ_B1
EQ_B0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ADN8102
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Type Description
1
RESET
Control Reset Input, Active Low
2
LOS_A
Digital I/O Port A Loss of Signal Status, Active Low
3 IN_A0 I/O High Speed Input Complement
4 IP_A0 I/O High Speed Input
5 VCC Power Positive Supply
6 IN_A1 I/O High Speed Input Complement
7 IP_A1 I/O High Speed Input
8 VTTI Power Input Termination Supply
9 IN_A2 I/O High Speed Input Complement
10 IP_A2 I/O High Speed Input
11 VEE Power Negative Supply
12 IN_A3 I/O High Speed Input Complement
13 IP_A3 I/O High Speed Input
14 DVCC Power Digital Power Supply
15 EQ_A1 Control Port A Input Equalization MSB
16 EQ_A0 Control Port A Input Equalization LSB
17 VEE Power Negative Supply
18 LB Control Loopback Control
19 ON_B0 I/O High Speed Output Complement
20 OP_B0 I/O High Speed Output
21 VCC Power Positive Supply
22 ON_B1 I/O High Speed Output Complement
23 OP_B1 I/O High Speed Output
24 VTTO Power Output Termination Supply
25 ON_B2 I/O High Speed Output Complement
26 OP_B2 I/O High Speed Output
27 VEE Power Negative Supply