Datasheet

ADN8102
Rev. B | Page 5 of 36
TIMING SPECIFICATIONS
Table 2. I
2
C Timing Parameters
Parameter Min Max Unit Description
f
SCL
0 400 kHz SCL clock frequency
t
HD:STA
0.6 Not applicable μs Hold time for a start condition
t
SU:STA
0.6 Not applicable μs Setup time for a repeated start condition
t
LOW
1.3 Not applicable μs Low period of the SCL clock
t
HIGH
0.6 Not applicable μs High period of the SCL clock
t
HD:DAT
0 Not applicable μs Data hold time
t
SU:DAT
10 Not applicable ns Data setup time
t
R
1 300 ns Rise time for both SDA and SCL
t
F
1 300 ns Fall time for both SDA and SCL
t
SU:STO
0.6 Not applicable μs Setup time for a stop condition
t
BUF
1 Not applicable ns Bus free time between a stop and a start condition
C
IO
5 7 pF Capacitance for each I/O pin
t
RESET
10 Not applicable ns Reset pulse width
1
1
Reset pulse width is defined as the time
RESET
is held below the logic low threshold (V
IL
) listed in Table 1 while the DV
CC
supply is within the operating range in Table 1.
07060-010
SPSrS
SDA
SCL
t
F
t
R
t
F
t
R
t
BUF
t
LOW
t
HD:STA
t
HD:DAT
t
HIGH
t
SU:DAT
t
SU:STA
t
SU:STO
t
HD:STA
Figure 2. I
2
C Timing Diagram
07060-103
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 5 10 15 20 25 30 35 40 45 50
VOLTAGE (V)
TIME (ns)
t
RESET
DVCC (V)
DVCC MAX LIMIT
DVCC MIN LIMIT
RESET
Figure 3. Reset Timing Diagram