Datasheet

ADN8102
Rev. B | Page 32 of 36
Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default
OUT_A
configuration
0xC0 EN
DATA
RATE
PE[2] PE[1] PE[0] 0x20
OUT_A
Output Level
Control 1
0xC1
PE CTL
SRC
OUTA_OLEV1[6:0] 0x40
OUT_A
Output Level
Control 0
0xC2 OUTA_OLEV0[6:0] 0x40
OUT_A
squelch
control
0xC3
SQUELCH[3:0] DISABLE[3:0]
0xFF
OUT_B
configuration
0xE0 EN
DATA
RATE
PE[2] PE[1] PE[0] 0x20
OUT_B
Output Level
Control 1
0xE1
PE CTL
SRC
OUTB_OLEV1[6:0] 0x40
OUT_B
Output Level
Control 0
0xE2 OUTB_OLEV0[6:0] 0x40
OUT_B
squelch
control
0xE3
SQUELCH[3:0] DISABLE[3:0]
0xFF
1
Read-only register.