Datasheet

ADN8102
Rev. B | Page 25 of 36
I
2
C CONTROL INTERFACE
SERIAL INTERFACE GENERAL FUNCTIONALITY
The ADN8102 register set is controlled through a 2-wire
I
2
C interface. The ADN8102 acts only as an I
2
C slave device.
Therefore, the I
2
C bus in the system needs to include an I
2
C
master to configure the ADN8102 and other I
2
C devices that
may be on the bus. Data transfers are controlled using the two
I
2
C wires: the SCL input clock pin and the SDA bidirectional
data pin.
The ADN8102 I
2
C interface can be run in the standard (100 kHz)
and fast (400 kHz) modes. The SDA line only changes value
when the SCL pin is low with two exceptions. To indicate the
beginning or continuation of a transfer, the SDA pin is driven
low while the SCL pin is high, and to indicate the end of a
transfer, the SDA line is driven high while the SCL line is high.
Therefore, it is important to control the SCL clock to toggle
only when the SDA line is stable, unless indicating a start,
repeated start, or stop condition.
I
2
C INTERFACE DATA TRANSFERS—DATA WRITE
To write data to the ADN8102 register set, a microcontroller, or
any other I
2
C master, needs to send the appropriate control signals
to the ADN8102 slave device. The steps that need to be completed
are listed as follows, where the signals are controlled by the I
2
C
master, unless otherwise specified. A diagram of the procedure
can be seen in Figure 42.
1. Send a start condition (while holding the SCL line high,
pull the SDA line low).
2. Send the ADN8102 part address (seven bits) whose upper
five bits are the static value 10010b and whose lower two
bits are controlled by the ADDR[1:0] input pins. This transfer
should be MSB first.
3. Send the write indicator bit (0).
4. Wait for the ADN8102 to acknowledge the request.
5. Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
6. Wait for the ADN8102 to acknowledge the request.
7. Send the data (eight bits) to be written to the register whose
address was set in Step 5. This transfer should be MSB first.
8. Wait for the ADN8102 to acknowledge the request.
9a. Send a stop condition (while holding the SCL line high,
pull the SDA line high) and release control of the bus.
9b. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 2 in
this procedure to perform another write.
9c. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 2 of
the read procedure (in the I2C Interface Data Transfers—
Data Read section) to perform a read from another address.
9d. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 8 of
the read procedure (in the I2C Interface Data Transfers—
Data Read section) to perform a read from the same
address set in Step 5.
Figure 42 shows the ADN8102 write process. The SCL signal is
shown along with a general write operation and a specific example.
In the example, Data 0x92 is written to Address 0x6D of an
ADN8102 part with a part address of 0x4B. The part address is
seven bits wide. The upper five bits of the ADN8102 are internally
set to 10010b. The lower two bits are controlled by the ADDR[1:0]
pins. In this example, the bits controlled by the ADDR[1:0] pins
are set to 11b. In Figure 42, the corresponding step number is
visible in the circle under the waveform. The SCL line is driven by
the I
2
C master and never by the ADN8102 slave. As for the SDA
line, the data in the shaded polygons is driven by the ADN8102,
whereas the data in the nonshaded polygons is driven by the I
2
C
master. The end phase case shown is that of Step 9a.
Note that the SDA line only changes when the SCL line is low,
except for the case of sending a start, stop, or repeated start
condition, Step 1 and Step 9 in this case.
1
SCL
SDA
SDA
G
ENERAL CASE
EXAMPLE
START REGISTER ADDR
ACK ACK ACK
STOPDATA
R/W
FIXED PART ADDR
ADDR
[1:0]
2 2 3 4 5 6 7 8 9a
0
7060-008
Figure 42. I
2
C Write Diagram