Datasheet

ADN8102
Rev. B | Page 19 of 36
Table 10. LOS Threshold and Hysteresis Control Registers
Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default
IN_A/IN_B
LOS threshold
0x81,
0xA1
THRESH[6] THRESH[5] THRESH[4] THRESH[3] THRESH[2] THRESH[1] THRESH[0] 0x04
IN_A/IN_B
LOS hysteresis
0x82,
0xA2
HYST[6] HYST[5] HYST[4] HYST[3] HYST[2] HYST[1] HYST[0] 0x12
Table 11. LOS Status Registers
Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IN_A/IN_B
LOS status
0x1F,
0x3F
STICKY
LOS[3]
STICKY
LOS[2]
STICKY
LOS[1]
STICKY LOS[0]
REAL-TIME
LOS[3]
REAL-TIME
LOS[2]
REAL-TIME
LOS[1]
REAL-TIME
LOS[0]