Datasheet

ADN8102
Rev. B | Page 11 of 36
50Ω CABLES
2 2
TP3
HIGH SPEED
SAMPLING
OSCILLOSCOPE
50Ω CABLES
2 2
50Ω
ADN8102
AC-COUPLED
EVALUATION
BOARD
INPUT
PIN
OUTPUT
PIN
PATTERN
GENERATOR
DATA OUT
TP1
50Ω CABLES
2 2
TP2
30m CX4 CABLE
07060-021
50ps/DIV
200mV/DI
V
REFERENCE EYE DIAGRAM AT TP1
Figure 15. Input Equalization Test Circuit, CX4
07060-022
50ps/DIV
200mV/DI
V
Figure 16. 3.25 Gbps Input Eye, 30 Meters CX4 Cable (TP2 from Figure 15)
07060-023
50ps/DIV
200mV/DI
V
Figure 17. 3.75 Gbps Input Eye, 30 Meters CX4 Cable (TP2 from Figure 15)
07060-024
50ps/DIV
200mV/DI
V
Figure 18. 3.25 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting
(TP3 from Figure 15)
07060-025
50ps/DIV
200mV/DI
V
Figure 19. 3.75 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting
(TP3 from Figure 15)