Datasheet

ADN8102
Rev. B | Page 10 of 36
50Ω CABLES
2 2
TP3
HIGH SPEED
SAMPLING
OSCILLOSCOPE
50Ω CABLES
2 2
50Ω
ADN8102
AC-COUPLED
EVALUATION
BOARD
INPUT
PIN
OUTPUT
PIN
PATTERN
GENERATOR
DATA OUT
TP1
50Ω CABLES
2 2
TP2
FR4 TEST BACKPLANE
DIFFERENTIAL
STRIPLINE TRACES
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
TRACE LENGTHS = 40''
07060-016
50ps/DIV
200mV/DI
V
REFERENCE EYE DIAGRAM AT TP1
Figure 10. Input Equalization Test Circuit, FR4
07060-017
50ps/DIV
200mV/DI
V
Figure 11. 3.25 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 10)
07060-018
50ps/DIV
200mV/DI
V
Figure 12. 3.75 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 10)
07060-019
50ps/DIV
200mV/DI
V
Figure 13. 3.25 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting
(TP3 from Figure 10)
07060-020
50ps/DIV
200mV/DI
V
Figure 14. 3.75 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting
(TP3 from Figure 10)