Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - customised LFCSP 64 VQ

3.75 Gbps Quad Bidirectional

CX4 E

ualizer

ADN8102

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Optimized for dc to 3.75 Gbps data

Programmable input equalization

Up to 22 dB boost at 1.875 GHz

Compensates up to 30 meters of CX4 cable up to 3.75 Gbps

Compensates up to 40 inches of FR4 up to 3.75 Gbps

Programmable output pre-emphasis/de-emphasis

Up to 12 dB boost at 1.875 GHz (3.75 Gbps)

Compensates up to 15 meters of CX4 cable up to 3.75 Gbps

Compensates up to 40 inches of FR4 up to 3.75 Gbps

Flexible 1.8 V to 3.3 V core supply

Per lane P/N pair inversion for routing ease

Low power: 125 mW/channel up to 3.75 Gbps

DC- or ac-coupled differential CML inputs

Programmable CML output levels

50 Ω on-chip termination

Loss-of-signal detection

Temperature range operation: −40°C to +85°C

Supports 8b10b, scrambled, or uncoded NRZ data

C control interface

64-lead LFCSP (QFN) package

APPLICATIONS

10GBase-CX4

HiGig™

InfiniBand®

1×, 2× Fibre Channel

XAUI™

Gigabit Ethernet over backplane or cable

CPRI™

50 Ω cables

FUNCTIONAL BLOCK DIAGRAM

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

TRANSMIT

PRE-EMPHASIS

RECEIVE

EQUALIZATION

2:1

CONTROL LOGIC

ADN8102

Ix_B[3:0]

LOS_B

Ox_A[3:0]

ADDR[1:0]

SCL

SDA

RESET

Ox_B[3:0]

LOS_A

Ix_A[3:0]

PE_A[1:0]

EQ_A[1:0]

EQ_B[1:0]

PE_B[1:0]

ENA

ENB

07060-001

Figure 1.

GENERAL DESCRIPTION

The ADN8102 is a quad, bidirectional, CX4 cable/backplane

equalizer with eight differential PECL-/CML-compatible inputs

with programmable equalization and eight differential CML

outputs with programmable output levels and pre-emphasis or

de-emphasis. The operation of this device is optimized for NRZ

data at rates up to 3.75 Gbps.

The receive inputs provide programmable equalization to

compensate for up to 30 meters of CX4 cable (24 AWG) or

40 inches of FR4, and programmable pre-emphasis to compensate

for up to 15 meters of CX4 cable (24 AWG) or 40 inches of FR4

at 3.75 Gbps. Each channel also provides programmable loss-of-

signal detection and loopback capability for system testing and

debugging.

The ADN8102 is controlled through toggle pins, an I

C® control

interface that provides more flexible control, or a combination of

both. Every channel implements an asynchronous path supporting

dc to 3.75 Gbps NRZ data, fully independent of other channels. The

ADN8102 has low latency and very low channel-to-channel skew.

The main application for the ADN8102 is to support switching

in chassis-to-chassis applications over CX4 or InfiniBand cables.

The ADN8102 is packaged in a 9 mm × 9 mm 64-lead LFCSP

(QFN) package and operates from −40°C to +85°C.

Summary of content (36 pages)

PAGE 1
3.75 Gbps Quad Bidirectional CX4 Equalizer ADN8102 Optimized for dc to 3.75 Gbps data Programmable input equalization Up to 22 dB boost at 1.875 GHz Compensates up to 30 meters of CX4 cable up to 3.75 Gbps Compensates up to 40 inches of FR4 up to 3.75 Gbps Programmable output pre-emphasis/de-emphasis Up to 12 dB boost at 1.875 GHz (3.75 Gbps) Compensates up to 15 meters of CX4 cable up to 3.75 Gbps Compensates up to 40 inches of FR4 up to 3.75 Gbps Flexible 1.8 V to 3.
PAGE 2
ADN8102 TABLE OF CONTENTS Features .............................................................................................. 1 Lane Inversion ............................................................................ 18 Applications ....................................................................................... 1 Loopback ..................................................................................... 20 Functional Block Diagram ......................................................
PAGE 3
ADN8102 SPECIFICATIONS VCC = 1.8 V, VEE = 0 V, VTTI = VTTO = VCC, RL = 50 Ω, differential output swing = 800 mV p-p differential, 3.75 Gbps, PRBS 27 − 1, TA = 25°C, unless otherwise noted. Table 1.
PAGE 4
ADN8102 Parameter Output Voltage Range Output Current Output Resistance Output Return Loss LOS CHARACTERISTICS Assert Level Deassert Level POWER SUPPLY Operating Range VCC DVCC VTTI VTTO Supply Current ITTO ICC LOGIC CHARACTERISTICS Input High, VIH Input Low, VIL Output High, VOH Output Low, VOL THERMAL CHARACTERISTICS Operating Temperature Range θJA 1 2 Test Conditions/Comments Single-ended absolute voltage level, TxHeadroom = 0; VL minimum Single-ended absolute voltage level, TxHeadroom = 0; VH maximum
PAGE 5
ADN8102 TIMING SPECIFICATIONS Table 2.
PAGE 6
ADN8102 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VCC to VEE VTTI VTTO Internal Power Dissipation Differential Input Voltage Logic Input Voltage Storage Temperature Range Lead Temperature Junction Temperature Rating 3.7 V VCC + 0.6 V VCC + 0.6 V 4.26 W 2.0 V VEE − 0.3 V < VIN < VCC + 0.6 V −65°C to +125°C 300°C 125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 7
ADN8102 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PE_A1 PE_A0 ENA OP_A0 ON_A0 VCC OP_A1 ON_A1 VTTO OP_A2 ON_A2 VEE OP_A3 ON_A3 ADDR1 ADDR0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR ADN8102 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCL SDA LOS_B IP_B0 IN_B0 VCC IP_B1 IN_B1 VTTI IP_B2 IN_B2 VEE IP_B3 IN_B3 EQ_B1 EQ_B0 NOTES 1. EXPOSED PAD MUST BE CONNECTED TO VEE. Figure 4. Pin Configuration Table 4.
PAGE 8
ADN8102 Pin No.
PAGE 9
ADN8102 TYPICAL PERFORMANCE CHARACTERISTICS 2 50Ω CABLES 2 INPUT PIN OUTPUT 2 PIN 50Ω CABLES 2 50Ω ADN8102 PATTERN GENERATOR AC-COUPLED EVALUATION BOARD TP1 TP2 HIGH SPEED SAMPLING OSCILLOSCOPE 07060-011 DATA OUT 50ps/DIV Figure 8. 3.25 Gbps Output Eye, No Channel (TP2 from Figure 5) 50ps/DIV Figure 7. 3.75 Gbps Input Eye (TP1 from Figure 5) 07060-015 50ps/DIV 07060-013 200mV/DIV 200mV/DIV Figure 6. 3.
PAGE 10
ADN8102 PATTERN GENERATOR 2 50Ω CABLES 2 FR4 TEST BACKPLANE 50Ω CABLES 2 2 DIFFERENTIAL STRIPLINE TRACES TP1 8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 40'' INPUT OUTPUT 2 PIN PIN 50Ω CABLES 2 50Ω ADN8102 TP2 AC-COUPLED EVALUATION BOARD TP3 HIGH SPEED SAMPLING OSCILLOSCOPE 07060-016 200mV/DIV DATA OUT 50ps/DIV REFERENCE EYE DIAGRAM AT TP1 50ps/DIV Figure 13. 3.25 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting (TP3 from Figure 10) 50ps/DIV Figure 12. 3.
PAGE 11
ADN8102 PATTERN GENERATOR 2 50Ω CABLES 2 30m CX4 CABLE 50Ω CABLES 2 2 INPUT OUTPUT 2 PIN PIN 50Ω CABLES 2 50Ω ADN8102 TP1 TP2 AC-COUPLED EVALUATION BOARD TP3 HIGH SPEED SAMPLING OSCILLOSCOPE 07060-021 200mV/DIV DATA OUT 50ps/DIV REFERENCE EYE DIAGRAM AT TP1 50ps/DIV Figure 18. 3.25 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting (TP3 from Figure 15) 50ps/DIV Figure 17. 3.
PAGE 12
ADN8102 PATTERN GENERATOR 2 50Ω CABLES 2 50Ω CABLES 2 INPUT OUTPUT 2 PIN PIN ADN8102 TP1 FR4 TEST BACKPLANE 2 50Ω CABLES 2 50Ω DIFFERENTIAL STRIPLINE TRACES TP2 8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 40'' AC-COUPLED EVALUATION BOARD TP3 HIGH SPEED SAMPLING OSCILLOSCOPE 07060-026 200mV/DIV DATA OUT 50ps/DIV REFERENCE EYE DIAGRAM AT TP1 50ps/DIV Figure 23. 3.25 Gbps Output Eye, 40 Inch FR4 Output Channel, PE = Best Setting (TP3 from Figure 20) 50ps/DIV Figure 22.
PAGE 13
ADN8102 200mV/DIV DATA OUT 2 50Ω CABLES 2 INPUT OUTPUT 2 PIN PIN 50Ω CABLES 2 15m CX4 CABLE 2 50Ω CABLES 2 50Ω ADN8102 PATTERN GENERATOR AC-COUPLED EVALUATION BOARD TP3 TP2 HIGH SPEED SAMPLING OSCILLOSCOPE 07060-031 TP1 50ps/DIV REFERENCE EYE DIAGRAM AT TP1 50ps/DIV Figure 28. 3.25 Gbps Output Eye, 15 Meters CX4 Cable, PE = Best Setting (TP3 from Figure 25) 50ps/DIV Figure 27. 3.75 Gbps Output Eye, 15 Meters CX4 Cable, PE = 0 (TP3 from Figure 25) Figure 29. 3.
PAGE 14
ADN8102 100 80 DETERMINISTIC JITTER (ps) DETERMINISTIC JITTER (ps) 70 60 50 40 30 20 80 60 VCC = 3.3V 40 VCC = 1.8V 20 0 20 60 40 DATA RATE (Hz) 0 1.0 07060-036 0 Figure 30. Deterministic Jitter vs. Data Rate 1.5 2.0 2.5 3.0 INPUT COMMON MODE (V) 3.5 4.0 07060-039 10 Figure 33. Deterministic Jitter vs. Input Common Mode 100 100 80 DETERMINISTIC JITTER (ps) DETERMINISTIC JITTER (ps) 90 70 60 50 40 30 20 80 60 40 20 0.5 1.0 1.5 2.0 DIFFERENTIAL INPUT SWING (V) 2.5 0 1.
PAGE 15
ADN8102 450000 100 400000 90 300000 tR/tF (ps) 250000 200000 80 tR/tF 70 150000 100000 60 0 –8 –6 –4 –2 0 2 JITTER (ps) 4 6 8 10 Figure 36. Random Jitter Histogram 50 –60 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 37. Rise Time (tR)/Fall Time (tF) vs. Temperature Rev.
PAGE 16
ADN8102 THEORY OF OPERATION The ADN8102 is a quad, bidirectional cable and backplane equalizer that provides both input equalization and output preemphasis on both the line card and cable sides of the device. The device supports full loopback and through connectivity of the two unidirectional half-links, each consisting of four differential signal pairs. The ADN8102 offers extensively programmable output levels and pre-emphasis as well as the ability to disable the output current.
PAGE 17
ADN8102 RECEIVERS Input Structure and Input Levels The ADN8102 receiver inputs incorporate 50 Ω termination resistors, ESD protection, and a multizero transfer function equalizer that can be optimized for backplane or cable operation. Each channel also provides a programmable LOS function that provides an interrupt that can be used to squelch or disable the associated output when the differential input voltage falls below the programmed threshold value.
PAGE 18
ADN8102 Table 8. Receive Equalizer Boost vs. Setting (CX4 and FR4 Optimized Maps) EQ_A[1:0] and EQ_B[1:0] Pins 0 1 2 3 1 IN_Ax/IN_Bx Configuration, EQ[2:0] X1 0 1 2 3 4 5 6 7 EQBY 1 0 0 0 0 0 0 0 0 Cable Optimized Typical CX4 Cable Boost (dB) Length (Meters) 1.5 <2 10 2 to 6 12 8 to 10 14 12 to 14 17 16 to 18 19 20 to 22 20 24 to 26 21 28 to 30 22 30 to 32 FR4 Optimized Typical FR4 Trace Boost (dB) Length (Inches) 1.5 <5 3.5 5 to 10 3.9 10 to 15 4.25 15 to 20 4.5 20 to 25 4.75 25 to 30 5.0 30 to 35 5.
PAGE 19
ADN8102 Table 10. LOS Threshold and Hysteresis Control Registers Name IN_A/IN_B LOS threshold IN_A/IN_B LOS hysteresis Address 0x81, 0xA1 0x82, 0xA2 Bit 7 Bit 6 THRESH[6] Bit 5 THRESH[5] Bit 4 THRESH[4] Bit 3 THRESH[3] Bit 2 THRESH[2] Bit 1 THRESH[1] Bit 0 THRESH[0] Default 0x04 HYST[6] HYST[5] HYST[4] HYST[3] HYST[2] HYST[1] HYST[0] 0x12 Table 11.
PAGE 20
ADN8102 Bit 0 represents loopback of the Port A inputs to the Port B outputs (cable side loopback). Bit 1 represents loopback of the Port B inputs to the Port A outputs (board side loopback), with high representing loopback for both bits. Bit 1 can be overridden by the LB pin if the pin mode register is set to enable loopback via external pin as shown in Table 5.
PAGE 21
ADN8102 pin control. Similar to the receiver settings, the ADN8102 allows joint control of all four channels in a transmit port. Table 15 summarizes the absolute output level, pre-emphasis level, and high frequency boost for each of the basic control settings and the typical length of the CX4 cable and FR4 trace that each setting compensates. TRANSMITTERS Output Structure and Output Levels The ADN8102 transmitter outputs incorporate 50 Ω termination resistors, ESD protection, and an output current switch.
PAGE 22
ADN8102 Table 17.
PAGE 23
ADN8102 VSW-DC (mV) 450 450 450 450 450 450 450 500 500 500 500 500 500 500 550 550 550 550 550 550 550 600 600 600 600 600 600 600 650 650 650 650 650 650 700 700 700 700 700 750 750 750 750 800 800 800 850 850 900 VSW-PE (mV) 450 550 650 750 850 950 1050 500 600 700 800 900 1000 1100 550 650 750 850 950 1050 1150 600 700 800 900 1000 1100 1200 650 750 850 950 1050 1150 700 800 900 1000 1100 750 850 950 1050 800 900 1000 850 950 900 VDPP-DC (mV) 900 900 900 900 900 900 900 1000 1000 1000 1000 1000 1000 1
PAGE 24
ADN8102 SELECTIVE SQUELCH AND DISABLE Each transmitter is equipped with output disable and output squelch controls. Disable is a full power-down state: the transmitter current is reduced to zero, and the output pins pull up to VTTO, but there is a delay of approximately 1 μs associated with re-enabling the transmitter. The output disable control is accessed through the EN bit (Bit 4) of the OUT_A/OUT_B configuration registers through the I2C control interface.
PAGE 25
ADN8102 I2C CONTROL INTERFACE 7. SERIAL INTERFACE GENERAL FUNCTIONALITY The ADN8102 register set is controlled through a 2-wire I2C interface. The ADN8102 acts only as an I2C slave device. Therefore, the I2C bus in the system needs to include an I2C master to configure the ADN8102 and other I2C devices that may be on the bus. Data transfers are controlled using the two I2C wires: the SCL input clock pin and the SDA bidirectional data pin. 8. 9a. 9b. 9c.
PAGE 26
ADN8102 I2C INTERFACE DATA TRANSFERS—DATA READ 13a. To read data from the ADN8102 register set, a microcontroller, or any other I2C master, needs to send the appropriate control signals to the ADN8102 slave device. The steps that need to be completed are listed as follows, where the signals are controlled by the I2C master, unless otherwise specified. A diagram of the procedure can be seen in Figure 43. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13c.
PAGE 27
ADN8102 APPLICATIONS INFORMATION OUTPUT COMPLIANCE TxHeadroom In low voltage applications, users must pay careful attention to both the differential and common-mode signal levels. The choice of output voltage swing, preemphasis setting, supply voltages (VCC and VTTO), and output coupling (ac or dc) affect peak and settled single-ended voltage swings and the commonmode shift measured across the output termination resistors. These choices also affect output current and, consequently, power consumption.
PAGE 28
ADN8102 Table 21. Output Compliance for AC-Coupled Outputs VSW-DC (mV) 200 200 200 200 200 200 200 300 300 300 300 300 300 300 400 400 400 400 400 400 400 600 600 600 600 600 600 600 VSW-PE (mV) 200 300 400 500 600 700 800 300 400 500 600 700 800 900 400 500 600 700 800 900 1000 600 700 800 900 1000 1100 1200 PE (dB) 0.00 3.52 6.02 7.96 9.54 10.88 12.04 0.00 2.50 4.44 6.02 7.36 8.52 9.54 0.00 1.94 3.52 4.86 6.02 7.04 7.96 0.00 1.34 2.50 3.52 4.44 5.26 6.
PAGE 29
ADN8102 Supply Sequencing PRINTED CIRCUIT BOARD (PCB) LAYOUT GUIDELINES The high speed differential inputs and outputs should be routed with 100 Ω controlled impedance, differential transmission lines. The transmission lines, either microstrip or stripline, should be referenced to a solid low impedance reference plane. An example of a PCB cross-section is shown in Figure 45.
PAGE 30
ADN8102 To effectively remove heat from the package and to enhance electrical performance, the thermal paddle must be soldered (bonded) to the PCB thermal paddle, preferably with minimum voids. However, eliminating voids may not be possible because of the presence of thermal vias and the large size of the thermal paddle for larger size packages. Also, outgassing during the reflow process may cause defects (splatter, solder balling) if the solder paste coverage is too big.
PAGE 31
ADN8102 REGISTER MAP Table 22.
PAGE 32
ADN8102 Name OUT_A configuration OUT_A Output Level Control 1 OUT_A Output Level Control 0 OUT_A squelch control OUT_B configuration OUT_B Output Level Control 1 OUT_B Output Level Control 0 OUT_B squelch control 1 Address 0xC0 Bit 7 0xC1 PE CTL SRC Bit 6 Bit 5 EN Bit 4 DATA RATE 0xC2 0xC3 Bit 1 PE[1] Bit 0 PE[0] EN 0x40 OUTA_OLEV0[6:0] 0x40 PE[2] DATA RATE PE CTL SRC Default 0x20 OUTA_OLEV1[6:0] 0xFF DISABLE[3:0] 0xE2 0xE3 Bit 2 PE[2] SQUELCH[3:0] 0xE0 0xE1 Bit 3 PE[1] PE[0]
PAGE 33
ADN8102 OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 8.75 BSC SQ (BOTTOM VIEW) 33 32 17 16 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.50 BSC *6.15 6.00 SQ 5.85 EXPOSED PAD 0.50 0.40 0.30 PIN 1 INDICATOR 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION 080108-B TOP VIEW 12° MAX 64 1 49 48 PIN 1 INDICATOR 1.00 0.
PAGE 34
ADN8102 NOTES Rev.
PAGE 35
ADN8102 NOTES Rev.
PAGE 36
ADN8102 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07060-0-10/10(B) Rev.