Datasheet
Data Sheet ADN4670
Rev. A | Page 5 of 12
250mV
250mV
80%
20%
5%
5%
t/2 t/2
DIFFERENTIAL OUTPUT SIGNAL
V
OD
= (Qx) – (Qx)
0V DIFFERENTIAL
08870-003
Figure 3. Test Criteria for f
CLK
, t
r
, t
f
, and V
OD
PROGRAMMING LOGIC AC CHARACTERISTICS
V
DD
= 2.375 V to 2.625 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit Conditions/Comments
Maximum Frequency at CK Input f
MAX
100 150 MHz
Setup Time, SI to CK t
SU
2 ns Time for which SI must not change before the CK 0-to-1 transition
Hold Time, CK to SI
t
H
1.5
ns
Time for which SI must not change after the CK 0-to-1 transition
EN to CK Removal Time t
REMOVAL
1.5 ns Removal time, EN to CK
Start-Up Time t
STARTUP
1 µs Start-up time after disable through SI
Minimum Clock Pulse Width t
W
3 ns
Logic Input High Level V
IH
2 V V
DD
= 2.5 V
Logic Input Low Level V
IL
0.8 V V
DD
= 2.5 V
High Level Logic Input Current, CK I
IH
−5 +5 µA V
I
= V
DD
High Level Logic Input Current, SI and EN +10 −30 µA V
I
= V
DD
Low Level Logic Input Current, CK
I
IL
−10
+30
µA
V
I
= GND
Low Level Logic Input Current, SI and EN −5 +5 µA V
I
= GND