Datasheet

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3 V LVDS Quad CMOS

Differential Line Receiver

ADN4668

Rev. A

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FEATURES

±15 kV ESD protection on receiver input pins

400 Mbps (200 MHz) switching rates

Flow-through pin configuration simplifies PCB layout

150 ps channel-to-channel skew (typical)

100 ps differential skew (typical)

2.7 ns maximum propagation delay

3.3 V power supply

High impedance outputs on power-down

Low power design (3 mW quiescent typical)

Interoperable with existing 5 V LVDS drivers

Accepts small swing (310 mV typical) differential

input signal levels

Supports open, short, and terminated input fail-safe

0 V to −100 mV threshold region

Conforms to TIA/EIA-644 LVDS standard

Industrial operating temperature range of −40°C to +85°C

Available in 16-lead surface-mount SOIC and 16-lead low

profile TSSOP package

APPLICATIONS

Point-to-point data transmission

Multidrop buses

Clock distribution networks

Backplane receivers

FUNCTIONAL BLOCK DIAGRAM

IN1+

GND

ADN4668

IN1–

IN2+

IN2–

IN3+

IN3–

IN4+

OUT1

OUT2

OUT3

OUT4

IN4–

07237-001

Figure 1.

GENERAL DESCRIPTION

The ADN4668 is a quad-channel CMOS, low voltage differential

signaling (LVDS) line receiver offering data rates of over 400 Mbps

(200 MHz) and ultralow power consumption. It features a flow-

through pin configuration for easy PCB layout and separation

of input and output signals.

The device accepts low voltage (310 mV typical) differential

input signals and converts them to a single-ended, 3 V TTL/CMOS

logic level.

The ADN4668 also offers active-high and active-low enable/disable

inputs (EN and

) that control all four receivers. They disable

the receivers and switch the outputs to a high impedance state.

This high impedance state allows the outputs of one or more

ADN4668s to be multiplexed together and reduces the quies-

cent power consumption to 3 mW typical.

The ADN4668 and its companion driver, the ADN4667, offer

a new solution to high speed, point-to-point data transmission

and a low power alternative to emitter-coupled logic (ECL) or

positive emitter-coupled logic (PECL).

Summary of content (12 pages)

PAGE 1
3 V LVDS Quad CMOS Differential Line Receiver ADN4668 ±15 kV ESD protection on receiver input pins 400 Mbps (200 MHz) switching rates Flow-through pin configuration simplifies PCB layout 150 ps channel-to-channel skew (typical) 100 ps differential skew (typical) 2.7 ns maximum propagation delay 3.
PAGE 2
ADN4668 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 Functional Block Diagram ..............................................................
PAGE 3
ADN4668 SPECIFICATIONS VDD = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. 1, 2 Table 1.
PAGE 4
ADN4668 AC CHARACTERISTICS VDD = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. 1, 2, 3, 4 Table 2.
PAGE 5
ADN4668 VCC S1 RL RINx+ ROUTx CL RINx– EN SIGNAL GENERATOR 50Ω EN NOTES 1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE. 2. S1 CONNECTED TO VCC FOR tPZL AND tPLZ MEASUREMENTS. 3. S1 CONNECTED TO GND FOR tPZH AND tPHZ MEASUREMENTS. 07237-004 GND Figure 4. Test Circuit for Receiver Enable/Disable Delay 3V EN WITH EN = GND OR OPEN CIRCUIT 1.5V 1.5V 0V 3V EN WITH EN = VCC 1.5V 1.5V 0V tPHZ 0.5V tPZH VOH 50% ROUTx WITH VID = +100mV GND VCC ROUTx WITH VID = –100mV 0.5V tPLZ tPZL Figure 5.
PAGE 6
ADN4668 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC to GND Input Voltage (RINx+, RINx−) to GND Enable Input Voltage (EN, EN) to GND Output Voltage (ROUTx) to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ MAX) Power Dissipation Thermal Impedance, θJA TSSOP Package SOIC Package Reflow Soldering Peak Temperature Pb-Free Rating −0.3 V to +4 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.
PAGE 7
ADN4668 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 EN RIN1– 1 RIN1+ 2 15 ROUT1 RIN2+ 3 ADN4668 14 ROUT2 RIN2– 4 TOP VIEW (Not to Scale) RIN3– 5 RIN3+ 6 11 ROUT3 RIN4+ 7 10 ROUT4 RIN4– 8 9 13 VCC EN 07237-006 12 GND Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 8
ADN4668 TYPICAL PERFORMANCE CHARACTERISTICS –0.06 ILOAD = –400µA TA = 25°C VID = 200mV 3.5 OUTPUT TRISTATE CURRENT, IOS (nA) 3.4 3.3 3.2 3.1 3.0 VOUT = 0V TA = 25°C –0.07 –0.08 –0.09 –0.10 –0.11 –0.12 –0.13 –0.14 –0.15 3.0 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) 07237-007 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) Figure 7. Output High Voltage, VOH vs. Power Supply Voltage, VCC Figure 10. Output Tristate Current, IOS vs.
PAGE 9
ADN4668 2.40 92.0 91.5 91.0 90.5 90.0 –40 –15 10 35 60 TA = 25°C VID = 200mV FREQ = 200MHz CL = 15pF 2.35 2.30 2.25 2.20 tPHLD 2.15 2.10 tPLHD 2.05 2.00 1.95 3.0 85 07237-016 92.5 DIFFERENTIAL PROPAGATION DELAY, tPLHD , tPHLD (ns) VCC = 3.3V VID = 200mV FREQ = 200MHz ALL CHANNELS SWITCHING 93.0 07237-022 POWER SUPPLY CURRENT, ICC (mA) 93.5 3.1 AMBIENT TEMPERATURE, TA (°C) Figure 13. Power Supply Current, ICC vs. Ambient Temperature, TA 3.5 3.6 tPHLD 2.20 tPLHD 2.15 2.10 2.
PAGE 10
ADN4668 80 20 0 –20 –40 –80 –40 07237-019 –60 –15 10 35 60 TA = 25°C VID = 200mV FREQ = 25MHz CL = 15pF TRANSITION TIME, tTLH, tTHL (ps) 510 500 tTHL 480 07237-020 470 460 3.0 3.1 3.2 3.3 3.4 tTLH 500 490 480 470 tTHL –15 10 35 60 80 Figure 21. Transition Time, tTLH, tTHL vs. Ambient Temperature, TA 520 490 510 AMBIENT TEMPERATURE, TA (°C) 550 530 520 450 –40 85 Figure 19. Differential Skew, tSKD vs.
PAGE 11
ADN4668 THEORY OF OPERATION The ADN4668 is a quad-channel line receiver for low voltage differential signaling. It takes a differential input signal of 310 mV typical and converts it into a single-ended 3 V TTL/ CMOS logic signal. A differential current input signal, received via a transmission medium such as a twisted pair cable, develops a voltage across a terminating resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 Ω.
PAGE 12
ADN4668 OUTLINE DIMENSIONS 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 9 16 1 6.20 (0.2441) 5.80 (0.2283) 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.