Datasheet

ADN4668
Rev. A | Page 5 of 12
R
OUTx
R
INx+
50Ω
C
L
EN
EN
SIGNAL
GENERATOR
R INx–
V
CC
GND
S1
NOTES
1. C
L
INCLUDES LOAD AND TEST JIG CAPACITANCE.
2. S1 CONNECTED TO V
CC
FOR t
PZL
AND t
PLZ
MEASUREMENTS.
3. S1 CONNECTED TO GND FOR
t
PZH
AND t
PHZ
MEASUREMENTS.
R
L
07237-004
Figure 4. Test Circuit for Receiver Enable/Disable Delay
3V
0V
3
V
0V
t
PLZ
t
PHZ
t
PZH
t
PZL
V
OH
GND
V
OL
V
CC
EN WITH EN = GND
OR OPEN CIRCUIT
EN WITH EN = V
CC
50%
50%
R
OUTx
WITH V
ID
= –100mV
R
OUTx
WITH V
ID
= +100mV
0.5V
1.5V
1.5V
0.5V
07237-005
1.5V
1.5V
Figure 5. Receiver Enable/Disable Delay Waveforms