Datasheet

ADN4668
Rev. A | Page 11 of 12
THEORY OF OPERATION
The ADN4668 is a quad-channel line receiver for low voltage
differential signaling. It takes a differential input signal of
310 mV typical and converts it into a single-ended 3 V TTL/
CMOS logic signal.
A differential current input signal, received via a transmission
medium such as a twisted pair cable, develops a voltage across
a terminating resistor, R
T
. This resistor is chosen to match the
characteristic impedance of the medium, typically around 100 Ω.
The differential voltage is detected by the receiver and converted
back into a single-ended logic signal.
When the noninverting receiver input, R
INx+
, is positive with
respect to the inverting input, R
INx−
(current flows through R
T
from R
INx+
to R
INx−
), R
OUTx
is high. When the noninverting receiver
input, R
IN+
, is negative with respect to the inverting input, R
INx−
(current flows through R
T
from R
INx−
to R
INx+
), R
OUTx
is low.
Using the ADN4667 as a driver, the received differential current
is between ±2.5 mA and ±4.5 mA (±3.1 mA typical), developing
between ±250 mV and ±450 mV across a 100 Ω termination
resistor. The received voltage is centered on the receiver offset
of 1.2 V. The noninverting receiver input is typically
(1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input
is (1.2 V − [310 mV/2]) = 1.045 V for Logic 1. For Logic 0, the
inverting and noninverting input voltages are reversed. Note
that because the differential voltage reverses polarity, the peak-to-
peak voltage swing across R
T
is twice the differential voltage.
Current-mode signaling offers considerable advantages over
voltage-mode signaling, such as the RS-422. The operating
current remains fairly constant with increased switching
frequency, whereas the operating current of voltage-mode
drivers increases exponentially in most cases. This increase is
caused by the overlap as internal gates switch between high and
low, causing currents to flow from V
CC
to ground. A current-
mode device reverses a constant current between its two outputs,
with no significant overlap currents.
This is similar to emitter-coupled logic (ECL) and positive emitter-
coupled logic (PECL), but without the high quiescent current of
ECL and PECL.
ENABLE INPUTS
The ADN4668 has active-high and active-low enable inputs that
put all the logic outputs into a high impedance state when disabled,
reducing device current consumption from 9 mA typical to 1 mA
typical. See Table 5 for a truth table of the enable inputs.
Table 5. Enable Inputs Truth Table
EN
EN
R
INx+
R
INx−
R
OUTx
High Low or Open 1.045 V 1.355 V 0
High Low or Open 1.355 V 1.045 V 1
Any other combination
of EN and EN
X X High-Z
APPLICATIONS INFORMATION
Figure 22 shows a typical application for point-to-point data
transmission using the ADN4667 as the driver and the ADN4668
as the receiver.
07237-023
D
IN
D
OUT
R
T
100Ω
EN
EN
1/4 ADN46681/4 ADN4667
R
INx+
R
INx–
D
OUTy+
D
OUTy–
GND
EN
EN
GND
Figure 22. Typical Application Circuit