Datasheet

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3 V LVDS Quad CMOS

Differential Line Driver

Data Sheet

ADN4667

Rev. B

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FEATURES

±15 kV ESD protection on output pins

400 Mbps (200 MHz) switching rates

Flow through pinout simplifies PCB layout

300 ps typical differential skew

400 ps maximum differential skew

1.7 ns maximum propagation delay

3.3 V power supply

±310 mV differential signaling

Low power dissipation (10 mW typical)

Interoperable with existing 5 V LVDS receivers

High impedance on LVDS outputs on power-down

Conforms to TIA/EIA-644 LVDS standards

Industrial operating temperature range: −40°C to +85°C

Available in surface-mount (SOIC) and low profile

TSSOP package

Qualified for automotive applications

APPLICATIONS

Backplane data transmission

Cable data transmission

Clock distribution

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The ADN4667 is a quad, CMOS, low voltage differential signaling

(LVDS) line driver offering data rates of over 400 Mbps (200 MHz)

and ultralow power consumption. It features a flow through

pinout for easy PCB layout and separation of input and output

signals.

The device accepts low voltage TTL/CMOS logic signals and

converts them to a differential current output of typically ±3.1 mA

for driving a transmission medium such as a twisted pair cable.

The transmitted signal develops a differential voltage of typi-

cally ±310 mV across a termination resistor at the receiving end.

This is converted back to a TTL/CMOS logic level by an LVDS

receiver, such as the ADN4668.

The ADN4667 also offers active high and active low enable/

disable inputs (EN and

). These inputs control all four drivers

and turn off the current outputs in the disabled state to reduce

the quiescent power consumption to typically 10 mW.

The ADN4667 and its companion LVDS receiver, the ADN4668,

offer a new solution to high speed, point-to-point data trans-

mission, and a low power alternative to emitter-coupled logic

(ECL) or positive emitter-coupled logic (PECL).

07032-001

ADN4667

OUT1+

OUT1–

IN1

OUT2+

OUT2–

IN2

OUT3+

OUT3–

IN3

OUT4+

OUT4–

IN4

GND

Summary of content (16 pages)

PAGE 1
FEATURES ±15 kV ESD protection on output pins 400 Mbps (200 MHz) switching rates Flow through pinout simplifies PCB layout 300 ps typical differential skew 400 ps maximum differential skew 1.7 ns maximum propagation delay 3.
PAGE 2
ADN4667 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................7 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................8 Functional Block Diagram ..............................................................
PAGE 3
Data Sheet ADN4667 SPECIFICATIONS VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. All typical values are given for VCC = +3.3 V, TA = +25°C. Table 1.
PAGE 4
ADN4667 Data Sheet AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL 1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. All typical values are given for VCC = +3.3 V, TA = +25°C. Table 2.
PAGE 5
Data Sheet ADN4667 3V DIN 1.5V 0V tPLHD tPHLD VOD DOUT– VOH 0V (DIFFERENTIAL) VOL DOUT+ 80% 0V VDIFF = DOUT+ – DOUT– tTLH 20% 07032-004 VDIFF tTHL Figure 4. Driver Propagation Delay and Transition Time Waveforms DOUT+ CL 50Ω VCC 1.2V 50Ω DIN DOUT– CL SIGNAL GENERATOR 50Ω 07032-005 EN EN Figure 5. Test Circuit for Driver Three-State Delay 3V EN WITH EN = GND OR OPEN CIRCUIT 1.5V 0V 3V EN WITH EN = VCC 1.5V 0V tPHZ tPZH DOUT+ WITH DIN = VCC OR DOUT– WITH DIN = GND VOH 50% 1.
PAGE 6
ADN4667 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC to GND Input Voltage (DIN) to GND Enable Input Voltage (EN, EN) to GND Output Voltage (DOUT+, DOUT−) to GND Short-Circuit Duration (DOUT+, DOUT−) to GND Industrial Operating Temperature Range Storage Temperature Range Junction Temperature (TJ max) Power Dissipation θJA Thermal Impedance TSSOP Package SOIC Package Reflow Soldering Peak Temperature (10sec) Rating −0.3 V to +4 V −0.3 V to VCC + 0.3 V −0.
PAGE 7
Data Sheet ADN4667 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 15 DOUT1+ DIN2 3 ADN4667 14 DOUT2+ VCC 4 TOP VIEW (Not to Scale) 13 DOUT2– 12 DOUT3– DIN3 6 11 DOUT3+ DIN4 7 10 DOUT4+ EN 8 9 DOUT4– GND 5 NC = NO CONNECT 07032-007 DOUT1– EN 1 DIN1 2 Figure 7. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 8
ADN4667 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 440 1.414 1.412 3.0 07032-008 1.413 3.1 3.2 3.3 3.4 3.5 TA = 25°C VIN = GND OR VCC 420 400 380 360 07032-011 TA = 25°C RL = 100Ω OUTPUT THREE-STATE CURRENT, IOZ (pA) OUTPUT HIGH VOLTAGE, VOH (V) 1.415 340 3.0 3.6 3.1 07032-009 1.088 3.2 3.3 3.4 3.5 DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV) OUTPUT LOW VOLTAGE, VOL (V) 325.0 1.089 3.1 324.6 324.4 324.2 3.1 3.4 3.5 3.6 3.5 450 400 350 300 250 90 3.
PAGE 9
Data Sheet 14.92 1.251 1.249 3.0 07032-014 1.250 3.1 3.2 3.3 3.4 3.5 14.91 14.90 VCC = 3.3V f = 1MHz CL = 15pF VIN = 0V TO 3V RL = 100Ω PER DRIVER 14.89 14.88 –40 3.6 –20 POWER SUPPLY VOLTAGE, VCC (V) ALL CHANNELS SWITCHING 20 18 16 ONE CHANNEL SWITCHING 10 100 1100 tPHLD tPLHD 1000 900 3.0 500 3.1 3.3 3.4 3.5 3.4 3.5 3.6 3.6 VCC = 3.3V f = 1MHz CL = 15pF RL = 100Ω PER DRIVER tPLHD 1100 tPHLD 1000 900 –40 07032-019 DIFFERENTIAL PROPAGATION DELAY (ns) 14.
PAGE 10
ADN4667 Data Sheet 400 TA = 25°C f = 1MHz CL = 15pF RL = 100Ω PER DRIVER TA = 25°C f = 1MHz CL = 15pF RL = 100Ω PER DRIVER TRANSITION TIME (ps) 80 60 40 380 tTLH 360 tTHL 340 0 3.0 3.1 3.2 3.3 3.4 3.5 320 3.0 3.6 07032-022 20 07032-020 DIFFERENTIAL SKEW, tSKD (ps) 100 3.1 POWER SUPPLY VOLTAGE, VCC (V) Figure 20. Differential Skew vs. Supply Voltage 400 VCC = 3.3V f = 1MHz CL = 15pF RL = 100Ω PER DRIVER TRANSITION TIME (ps) 40 3.3 3.4 3.5 3.6 Figure 22. Transition Time vs.
PAGE 11
Data Sheet ADN4667 THEORY OF OPERATION When DIN is high (Logic 1), current flows out of the DOUT+ pin (current source) through RT and back into the DOUT− pin (current sink). At the receiver, this current develops a positive differential voltage across RT (with respect to the inverting input) and gives a Logic 1 at the receiver output. When DIN is low, DOUT+ sinks current and DOUT− sources current; a negative differential voltage across RT gives a Logic 0 at the receiver output.
PAGE 12
ADN4667 Data Sheet OUTLINE DIMENSIONS 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 9 16 1 6.20 (0.2441) 5.80 (0.2283) 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.
PAGE 13
Data Sheet ADN4667 ORDERING GUIDE Model 1, 2 ADN4667ARZ ADN4667ARZ-REEL7 ADN4667ARUZ ADN4667ARUZ-REEL7 ADN4667WARZ-REEL7 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Standard Small Outline Package [SOIC_N] Package Option R-16 R-16
PAGE 14
ADN4667 Data Sheet NOTES Rev.
PAGE 15
Data Sheet ADN4667 NOTES Rev.