Datasheet

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3 V, LVDS, Quad CMOS

Differential Line Receiver

ADN4666

Rev. 0

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FEATURES

±8 kV ESD IEC 61000-4-2 contact discharge on receiver input pins

400 Mbps (200 MHz) switching rates

100 ps channel-to-channel skew (typical)

100 ps differential skew (typical)

3.3 ns propagation delay (maximum)

3.3 V power supply

High impedance outputs on power-down

Low power design (10 mW quiescent typical)

Interoperable with existing 5 V LVDS drivers

Accepts small swing (350 mV typical) differential

input signal levels

Supports open, short, and terminated input fail-safe

Conforms to TIA/EIA-644 LVDS standard

Industrial operating temperature range of −40°C to +85°C

Available in surface-mount SOIC package and low profile

TSSOP package

APPLICATIONS

Point-to-point data transmission

Multidrop buses

Clock distribution networks

Backplane receivers

FUNCTIONAL BLOCK DIAGRAM

OUT1

OUT2

IN1+

IN1–

IN2+

IN2–

OUT4

OUT3

IN4–

IN3–

IN4+

IN3+

GND

ADN4666

08097-001

Figure 1.

GENERAL DESCRIPTION

The ADN4666 is a quad-channel, CMOS low voltage differential

signaling (LVDS) line receiver offering data rates of over 400 Mbps

(200 MHz) and ultralow power consumption.

The device accepts low voltage (350 mV typical) differential

input signals and converts them to a single-ended, 3 V TTL/CMOS

logic level.

The ADN4666 also offers active high and active low enable/disable

inputs (EN and

) that control all four receivers. These inputs

disable the receivers and switch the outputs to a high impedance

state. Consequently, the outputs of one or more ADN4666

devices can be multiplexed together to reduce the quiescent

power consumption to 10 mW typical.

The ADN4666 and its companion driver, the ADN4665, offer

a new solution to high speed, point-to-point data transmission

and offer a low power alternative to emitter-coupled logic (ECL)

or positive emitter-coupled logic (PECL).

Summary of content (12 pages)

PAGE 1
3 V, LVDS, Quad CMOS Differential Line Receiver ADN4666 ±8 kV ESD IEC 61000-4-2 contact discharge on receiver input pins 400 Mbps (200 MHz) switching rates 100 ps channel-to-channel skew (typical) 100 ps differential skew (typical) 3.3 ns propagation delay (maximum) 3.
PAGE 2
ADN4666 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 Functional Block Diagram ..............................................................
PAGE 3
ADN4666 SPECIFICATIONS VCC = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. 1, 2 Table 1.
PAGE 4
ADN4666 TIMING SPECIFICATIONS VCC = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 2.
PAGE 5
ADN4666 RINx– 1.3V 0V (DIFFERENTIAL) 1.2V VID = 300mV p-p RINx+ 1.1V tPLHD tPHLD VOH 80% 1.5V 1.5V 20% 20% tTLH VOL tTHL 08097-003 ROUTx 80% Figure 3. Receiver Propagation Delay and Transition Time Waveforms VCC S1 RL RINx+ ROUTx CL RINx– EN SIGNAL GENERATOR 50Ω EN NOTES 1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE. 2. S1 CONNECTED TO VCC FOR tPZL AND tPLZ MEASUREMENTS. 3. S1 CONNECTED TO GND FOR tPZH AND tPHZ MEASUREMENTS. 08097-004 GND Figure 4.
PAGE 6
ADN4666 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC to GND Input Voltage (RINx+, RINx−) to GND Enable Input Voltage (EN, EN) to GND Output Voltage (ROUTx) to GND Industrial Operating Temperature Range Storage Temperature Range Maximum Junction Temperature (TJ MAX) θJA Thermal Impedance Power Dissipation Reflow Soldering Peak Temperature, Pb-Free Rating −0.3 V to +4 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.
PAGE 7
ADN4666 RIN1– 1 16 VCC 2 15 RIN4– RIN1+ ROUT1 3 EN 4 ROUT2 5 ADN4666 14 RIN4+ TOP VIEW (Not to Scale) 13 ROUT4 12 EN RIN2+ 6 11 ROUT3 RIN2– 7 10 RIN3+ GND 8 9 RIN3– 08097-006 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 8
ADN4666 80 200 70 150 60 3.6V SUPPLY 100 3.3V SUPPLY 3.6V SUPPLY 40 3V SUPPLY 50 30 0 3V SUPPLY –50 20 –100 10 –150 0 0.01 0.1 1 10 FREQUENCY (MHz) 100 1k –200 –0.1 Figure 7. Power Supply Current vs. Frequency 0.4 0.9 1.4 1.9 2.4 2.9 COMMON-MODE VOLTAGE (V) 3.4 3.9 08097-010 3.3V SUPPLY SKEW (ps) 50 08097-007 POWER SUPPLY CURRENT (mA) TYPICAL PERFORMANCE CHARACTERISTICS Figure 10. Skew vs. Common-Mode Voltage, 25°C 2.8 2.7 3 COMMON-MODE VIN (V) 3V SUPPLY 2.6 2.5 2.
PAGE 9
ADN4666 THEORY OF OPERATION A differential current input signal, received via a transmission medium such as a twisted pair cable, develops a voltage across a termination resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 Ω. The differential voltage is detected by the receiver and converted back into a single-ended logic signal.
PAGE 10
ADN4666 OUTLINE DIMENSIONS 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 9 16 1 6.20 (0.2441) 5.80 (0.2283) 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.
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ADN4666 NOTES Rev.