Datasheet

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ADN4666

Rev. 0 | Page 7 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IN1+

IN2+

IN2–

IN4+

IN3+

IN3–

IN1–

IN4–

OUT1

OUT2

OUT4

OUT3

GND

ADN4666

TOP VIEW

(Not to Scale)

08097-006

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 R

IN1−

Receiver Channel 1 Inverting Input. When this input is more negative than R

IN1+

, R

OUT1

is high. When this input is

more positive than R

IN1+

, R

OUT1

is low.

2 R

IN1+

Receiver Channel 1 Noninverting Input. When this input is more positive than R

IN1−

, R

OUT1

is high. When this input

is more negative than R

IN1−

, R

OUT1

is low.

3 R

OUT1

Receiver Channel 1 Output (3 V TTL/CMOS). If the differential input voltage between R

IN1+

and R

IN1−

is positive, this

output is high. If the differential input voltage is negative, this output is low.

4 EN

Active High Enable and Power-Down Input (3 V TTL/CMOS). When EN is low and

is high, the receiver outputs

are disabled and are in a high impedance state. When EN is high and

is low or when EN is low and

is low,

the receiver outputs are enabled. When EN is high and

is high, the receiver outputs are enabled.

5 R

OUT2

Receiver Channel 2 Output (3 V TTL/CMOS). If the differential input voltage between R

IN2+

and R

IN2−

is positive, this

output is high. If the differential input voltage is negative, this output is low.

6 R

IN2+

Receiver Channel 2 Noninverting Input. When this input is more positive than R

IN2−

, R

OUT2

is high. When this input

is more negative than R

IN2−

, R

OUT2

is low.

7 R

IN2−

Receiver Channel 2 Inverting Input. When this input is more negative than R

IN2+

, R

OUT2

is high. When this input is

more positive than R

IN2+

, R

OUT2

is low.

8 GND Ground Reference Point for All Circuitry on the Part.

9 R

IN3−

Receiver Channel 3 Inverting Input. When this input is more negative than R

IN3+

, R

OUT3

is high. When this input is

more positive than R

IN3+

, R

OUT3

is low.

10 R

IN3+

Receiver Channel 3 Noninverting Input. When this input is more positive than R

IN3−

, R

OUT3

is high. When this input

is more negative than R

IN3−

, R

OUT3

is low.

11 R

OUT3

Receiver Channel 3 Output (3 V TTL/CMOS). If the differential input voltage between R

IN3+

and R

IN3−

is positive, this

output is high. If the differential input voltage is negative, this output is low.

Active Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). ). When EN is low and

is high, the

receiver outputs are disabled and are in a high impedance state. When EN is high and

is low or when EN is low

and

is low, the receiver outputs are enabled. When EN is high and

is high, the receiver outputs are enabled.

13 R

OUT4

Receiver Channel 4 Output (3 V TTL/CMOS). If the differential input voltage between R

IN4+

and R

IN4−

is positive, this

output is high. If the differential input voltage is negative, this output is low.

14 R

IN4+

Receiver Channel 4 Noninverting Input. When this input is more positive than R

IN4−

, R

OUT4

is high. When this input

is more negative than R

IN4−

, R

OUT4

is low.

15 R

IN4−

Receiver Channel 4 Inverting Input. When this input is more negative than R

IN4+

, R

OUT4

is high. When this input is

more positive than R

IN4+

, R

OUT4

is low.

16 V

Power Supply Input. The ADN4666 can be operated from 3.0 V to 3.6 V.