Datasheet

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3 V, LVDS, Quad, CMOS

Differential Line Driver

ADN4665

Rev. 0

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FEATURES

±15 kV ESD protection on output pins

400 Mbps (200 MHz) switching rates

100 ps typical differential skew

400 ps maximum differential skew

2 ns maximum propagation delay

3.3 V power supply

±350 mV differential signaling

Low power dissipation (13 mW typical)

Interoperable with existing 5 V LVDS receivers

High impedance on LVDS outputs on power-down

Conforms to TIA/EIA-644 LVDS standards

Industrial operating temperature range: −40°C to +85°C

Available in surface-mount SOIC package and low profile

TSSOP package

APPLICATIONS

Backplane data transmission

Cable data transmission

Clock distribution

FUNCTIONAL BLOCK DIAGRAM

OUT1+

OUT1–

OUT2+

OUT2–

OUT3+

OUT4+

IN4

OUT4–

OUT3–

IN1

IN2

IN3

GND

ADN4665

08085-001

Figure 1.

GENERAL DESCRIPTION

The ADN4665 is a quad-channel, CMOS, low voltage differential

signaling (LVDS) line driver offering data rates of over 400 Mbps

(200 MHz) and ultralow power consumption.

The device accepts low voltage TTL/CMOS logic signals and

converts them to a differential current output of typically ±3.5 mA

for driving a transmission medium such as a twisted pair cable.

The transmitted signal develops a differential voltage of typi-

cally ±350 mV across a termination resistor at the receiving end.

This voltage is converted back to a TTL/CMOS logic level by an

LVDS receiver.

The ADN4665 also offers active high and active low enable/

disable inputs (EN and

). These inputs control all four drivers

and turn off the current outputs in the disabled state to reduce

the quiescent power consumption to typically 10 mW.

The ADN4665 offers a new solution to high speed, point-to-point

data transmission and offers a low power alternative to emitter-

coupled logic (ECL) or positive emitter-coupled logic (PECL).

Summary of content (12 pages)

PAGE 1
3 V, LVDS, Quad, CMOS Differential Line Driver ADN4665 ±15 kV ESD protection on output pins 400 Mbps (200 MHz) switching rates 100 ps typical differential skew 400 ps maximum differential skew 2 ns maximum propagation delay 3.
PAGE 2
ADN4665 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 Functional Block Diagram ..............................................................
PAGE 3
ADN4665 SPECIFICATIONS VCC = 3.0 V to 3.6 V, RL = 100 Ω, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. All typical values are given for VCC = 3.3 V, TA = 25°C. Table 1.
PAGE 4
ADN4665 TIMING CHARACTERISTICS VCC = 3.0 V to 3.6 V, RL = 100 Ω, CL 1 = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. All typical values are given for VCC = 3.3 V, TA = 25°C. Table 2.
PAGE 5
ADN4665 3V DINx 1.5V 0V tPLHD tPHLD VOD DOUTx– VOH 0V (DIFFERENTIAL) VOL DOUTx+ 80% 0V VDIFF 20% tTLH 08085-004 VDIFF = DOUTx+ – DOUTx– tTHL Figure 4. Driver Propagation Delay and Transition Time Waveforms VCC DOUTx+ CL VCC 50Ω 1.2V DINx 50Ω S1 DOUTx– CL EN SIGNAL GENERATOR 50Ω EN 08085-005 NOTES 1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE. 2. S1 CONNECTED TO VCC FOR tPHZ AND tPZH TEST. 3. S1 CONNECTED TO GND FOR tPLZ AND tPZL TEST. Figure 5.
PAGE 6
ADN4665 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC to GND Input Voltage (DINx) to GND Enable Input Voltage (EN, EN) to GND Output Voltage (DOUTx+, DOUTx−) to GND Short-Circuit Duration (DOUTx+, DOUTx−) to GND Industrial Operating Temperature Range Storage Temperature Range Junction Temperature (TJ max) Power Dissipation θJA Thermal Impedance TSSOP Package SOIC Package Reflow Soldering Peak Temperature (10 sec) Rating −0.3 V to +4 V −0.3 V to VCC + 0.3 V −0.
PAGE 7
ADN4665 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DIN1 1 16 VCC DOUT1+ 2 15 DIN4 DOUT1– 3 14 DOUT4+ ADN4665 13 DOUT4– TOP VIEW DOUT2– 5 (Not to Scale) 12 EN DOUT2+ 6 11 DOUT3– DIN2 7 10 DOUT3+ GND 8 9 DIN3 08085-007 EN 4 Figure 7. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 8
ADN4665 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 2.0 VCC = 3.3V TA = 25°C VCC = 3.0V TO 3.6V TA = 25°C 1.8 DOUTx+ = +3.3V 2.5 1.6 DOUTx+ DOUT (V) DOUT (V) 2.0 1.5 DOUT = +3.0V DOUT = +3.3V DOUT = +3.6V DOUT = –3.0V DOUT = –3.3V DOUT = –3.6V 1.4 1.2 DOUTx– 1.0 1.0 0.5 0 1 2 3 4 5 6 7 RL (kΩ) 0.6 08085-008 0 0 Figure 8. Single-Ended Driver Output Voltage vs. Load Resistance 50 100 150 200 RL (Ω) 250 300 Figure 9. Driver Output vs. Load Resistance Rev.
PAGE 9
ADN4665 THEORY OF OPERATION The ADN4665 is a quad line driver for low voltage differential signaling. It takes a single-ended 3 V logic signal and converts it to a differential current output. The data can then be transmitted for considerable distances, over media such as a twisted pair cable or PCB backplane, to an LVDS receiver such as the ADN4666, where it develops a voltage across a termination resistor, RT.
PAGE 10
ADN4665 OUTLINE DIMENSIONS 10.00 (0.3937) 9.80 (0.3858) 9 16 4.00 (0.1575) 3.80 (0.1496) 1 6.20 (0.2441) 5.80 (0.2283) 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.
PAGE 11
ADN4665 NOTES Rev.