Datasheet

ADN4665
Rev. 0 | Page 5 of 12
D
INx
V
DIFF
t
PLHD
t
PHLD
V
DIFF
= D
OUTx+
–D
OUTx–
V
OH
V
OL
V
OD
3
V
1.5V
0V (DIFFERENTIAL)
0V
80%
20%
0V
D
OUTx+
D
OUTx–
t
TLH
t
THL
08085-004
Figure 4. Driver Propagation Delay and Transition Time Waveforms
SIGNAL
GENERATOR
NOTES
1.
C
L
INCLUDES LOAD AND TEST JIG CAPACITANCE.
2. S1 CONNECTED TO V
CC
FOR t
PHZ
AND t
PZH
TEST.
3. S1 CONNECTED TO GND FOR
t
PLZ
AND t
PZL
TEST.
V
CC
V
CC
S1
50Ω
50Ω
50Ω
1.2V
D
INx
D
OUTx+
D
OUTx–
C
L
C
L
EN
EN
08085-005
Figure 5. Test Circuit for Driver Three-State Delay
D
OUTx+
WITH D
INx
= V
CC
OR D
OUTx–
WITH D
INx
= GND
D
OUTx+
WITH D
INx
= GND
OR D
OUTx–
WITH D
INx
= V
CC
3
V
1.5V
50%
50%
0V
3V
1.5V
0V
V
OH
V
OL
1.2V
1.2V
EN WITH EN = GND
OR OPEN CIRCUIT
EN WITH EN = V
CC
t
PZH
t
PHZ
t
PLZ
t
PZL
0
8085-006
Figure 6. Driver Three-State Delay Waveforms