Datasheet

ADN4664
Rev. 0 | Page 5 of 12
Test Circuits and Timing Diagrams
V
CC
R
OUTx
R
INx+
C
L
SIGNAL
GENERATOR
50Ω 50Ω
R
INx–
C
L
= LOAD AND TEST JIG CAPACITANCE
RECEIVER IS
ENABLED
0
7961-002
Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time
20%
80%
80%
20%
1.5V
1.5V
t
PLHD
t
PHLD
R
INx–
R
INx+
0V (DIFFERENTIAL)
t
TLH
t
THL
V
OH
V
OL
1.2V
1.3V
1.1V
R
OUTx
V
ID
= 200mV
07961-003
Figure 3. Receiver Propagation Delay and Transition Time Waveforms