Datasheet

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Dual, 3 V, CMOS, LVDS

Differential Line Receiver

ADN4664

Rev. 0

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FEATURES

±15 kV ESD protection on output pins

400 Mbps (200 MHz) switching rates

Flow-through pinout simplifies PCB layout

100 ps channel-to-channel skew (typical)

2.5 ns maximum propagation delay

3.3 V power supply

High impedance outputs on power-down

Low power design: typically 3 mW (quiescent)

Interoperable with existing 5 V LVDS drivers

Accepts small swing (310 mV typical) differential signal

levels

Supports open, short, and terminated input fail-safe

0 V to −100 mV threshold region

Conforms to TIA/EIA-644 LVDS standard

Industrial operating temperature range: −40°C to +85°C

Available in surface-mount (SOIC) package

APPLICATIONS

Point-to-point data transmission

Multidrop buses

Clock distribution networks

Backplane receivers

FUNCTIONAL BLOCK DIAGRAM

OUT1

IN1+

IN1–

ADN4664

GND

OUT2

IN2+

IN2–

07961-001

Figure 1.

GENERAL DESCRIPTION

The ADN4664 is a dual, CMOS, low voltage differential

signaling (LVDS) line receiver offering data rates of over

400 Mbps (200 MHz) and ultralow power consumption.

It features a flow-through pinout for easy PCB layout and

separation of input and output signals.

The device accepts low voltage (310 mV typical) differential

input signals and converts them to a single-ended 3 V TTL/

CMOS logic level.

The ADN4664 and its companion driver, the ADN4663, offer a

new solution to high speed, point-to-point data transmission,

and a low power alternative to emitter-coupled logic (ECL) or

positive emitter-coupled logic (PECL).

Summary of content (12 pages)

PAGE 1
Dual, 3 V, CMOS, LVDS Differential Line Receiver ADN4664 ±15 kV ESD protection on output pins 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 100 ps channel-to-channel skew (typical) 2.5 ns maximum propagation delay 3.
PAGE 2
ADN4664 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 General Description .........................................................................
PAGE 3
ADN4664 SPECIFICATIONS VDD = 3.0 V to 3.6 V; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 LVDS INPUT High Threshold at RINx+, RINx− 3 Low Threshold at RINx+, RINx−3 Input Current at RINx+, RINx− OUTPUT Output High Voltage Output Low Voltage Output Short-Circuit Current 4 Input Clamp Voltage POWER SUPPLY No Load Supply Current ESD PROTECTION RINx+, RINx− Pins All Pins Except RINx+, RINx− Symbol VTH VTL IIN VOH VOL IOS VCL ICC Min −100 −10 −10 −20 2.
PAGE 4
ADN4664 AC CHARACTERISTICS VDD = 3.0 V to 3.6 V; CL 1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew |tPHLD − tPLHD| 4 Differential Channel-to-Channel Skew (Same Device) 5 Differential Part-to-Part Skew 6 Differential Part-to-Part Skew 7 Rise Time Fall Time Maximum Operating Frequency 8 Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL fMAX Min 1.
PAGE 5
ADN4664 Test Circuits and Timing Diagrams VCC RINx+ SIGNAL GENERATOR ROUTx RINx– 50Ω 50Ω CL 07961-002 RECEIVER IS ENABLED CL = LOAD AND TEST JIG CAPACITANCE Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time RINx– 1.3V 0V (DIFFERENTIAL) VID = 200mV 1.2V RINx+ 1.1V tPLHD tPHLD VOH 80% 1.5V 1.5V 20% 20% tTLH tTHL Figure 3. Receiver Propagation Delay and Transition Time Waveforms Rev.
PAGE 6
ADN4664 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC to GND Input Voltage (RINx+, RINx−) to GND Output Voltage (ROUTx) to GND Operating Temperature Range Industrial Temperature Range Storage Temperature Range Junction Temperature (TJ max) Power Dissipation SOIC Package θJA Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating −0.3 V to +4 V −0.3 V to VCC + 3.9 V −0.3 V to VCC + 0.
PAGE 7
ADN4664 RIN1– 1 RIN1+ 2 RIN2+ 3 ADN4664 TOP VIEW RIN2– 4 (Not to Scale) 8 VCC 7 ROUT1 6 ROUT2 5 GND 07961-004 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic RIN1− 2 RIN1+ 3 RIN2+ 4 RIN2− 5 6 GND ROUT2 7 ROUT1 8 VCC Description Receiver Channel 1 Inverting Input. When this input is more negative than RIN1+, ROUT1 is high. When this input is more positive than RIN1+, ROUT1 is low.
PAGE 8
ADN4664 TYPICAL PERFORMANCE CHARACTERISTICS 0 3.6 ILOAD = –400µA TA = 25°C VID = 200mV 3.4 3.3 3.2 3.1 3.0 –10 –15 –20 –25 –30 –35 –40 –45 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) 07961-007 3.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) Figure 5. Output High Voltage vs. Power Supply Voltage Figure 8. Threshold Voltage vs. Power Supply Voltage 33.60 50 45 POWER SUPPLY CURRENT, ICC (mA) 33.55 33.50 33.45 33.40 33.35 33.30 40 TA = 25°C VCC = 3.
PAGE 9
ADN4664 6.0 2.3 tPHLD 2.2 2.1 tPLHD 2.0 1.9 1.8 –40 –15 10 35 60 85 AMBIENT TEMPERATURE, TA (°C) Figure 11. Differential Propagation Delay vs. Ambient Temperature 4.5 4.0 3.5 3.0 tPHLD 2.0 1.5 0.5 1.0 1.5 2.0 2.5 DIFFERENTIAL INPUT VOLTAGE, VID (V) 3.0 Figure 14. Differential Propagation Delay vs. Differential Input Voltage 250 3.0 2.5 tPLHD tPHLD 0 0.5 1.0 1.5 150 100 50 0 –50 2.0 3.0 2.5 –100 3.1 3.2 3.3 3.4 3.5 3.6 85 POWER SUPPLY VOLTAGE, VCC (V) Figure 15.
PAGE 10
ADN4664 1800 580 VCC = 3.3V VID = 200mV 560 FREQUENCY = 25MHz CL = 15pF 540 tTLH 520 500 480 460 TA = 25°C VCC = 3.3V VID = 200mV FREQUENCY = 1MHz 1600 TRANSITION TIME, tTLH, tTHL (ps) tTHL 440 1400 1200 1000 tTLH 800 tTHL 600 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) 200 07961-020 400 3.0 07961-027 400 420 10 30 35 40 45 40 45 2.9 DIFFERENTIALPROPAGATIONDELAY, tPLHD , tPHLD (ns) VCC = 3.
PAGE 11
ADN4664 THEORY OF OPERATION A differential current input signal, received via a transmission medium, such as a twisted pair cable, develops a voltage across a terminating resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 Ω. The differential voltage is detected by the receiver and converted back into a single-ended logic signal.
PAGE 12
ADN4664 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 1 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.