Datasheet

ADN4663
Rev. 0 | Page 5 of 12
Test Circuits and Timing Diagrams
V
CC
D
OUTx+
D
OUTx–
D
INx
V
OS
V
OD
R
L
/2
R
L
/2
V
CC
VV
07927-002
Figure 2. Test Circuit for Driver V
OD
and V
OS
V
CC
D
OUTx+
D
OUTx–
D
INx
50Ω
C
L
INCLUDES LOAD AND TEST JIG CAPACITANCE.
SIGNAL
GENERATOR
C
L
C
L
R
L
07927-003
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
20%
80%
0V
20%
0V
80%
1.5V
3
V
1.5V
t
PLHD
D
INx
D
OUTx–
D
OUTx+
V
DIFF
0V (DIFFERENTIAL)
0V
t
PHLD
t
THL
t
THL
0V
V
OH
V
OL
V
DIFF
= D
OUT+
– D
OUT–
V
OD
07927-004
Figure 4. Driver Propagation Delay and Transition Time Waveforms