Datasheet

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Dual, 3 V, CMOS, LVDS

High Speed Differential Driver

ADN4663

Rev. 0

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FEATURES

±15 kV ESD protection on output pins

600 Mbps (300 MHz) switching rates

Flow-through pinout simplifies PCB layout

300 ps typical differential skew

700 ps maximum differential skew

1.5 ns maximum propagation delay

3.3 V power supply

±355 mV differential signaling

Low power dissipation: 23 mW typical

Interoperable with existing 5 V LVDS receivers

Conforms to TIA/EIA-644 LVDS standard

Industrial operating temperature range (−40°C to +85°C)

Available in surface-mount (SOIC) package

APPLICATIONS

Backplane data transmission

Cable data transmission

Clock distribution

FUNCTIONAL BLOCK DIAGRAM

IN1

OUT1+

OUT1–

ADN4663

IN2

OUT2+

OUT2–

GND

07927-001

Figure 1.

GENERAL DESCRIPTION

The ADN4663 is a dual, CMOS, low voltage differential

signaling (LVDS) line driver offering data rates of over

600 Mbps (300 MHz), and ultralow power consumption.

It features a flow-through pinout for easy PCB layout and

separation of input and output signals.

The device accepts low voltage TTL/CMOS logic signals and

converts them to a differential current output of typically

±3.1 mA for driving a transmission medium such as a

twisted-pair cable. The transmitted signal develops a differential

voltage of typically ±355 mV across a termination resistor at the

receiving end, and this is converted back to a TTL/CMOS logic

level by a line receiver.

The ADN4663 and a companion receiver offer a new solution

to high speed point-to-point data transmission, and a low

power alternative to emitter-coupled logic (ECL) or positive

emitter-coupled logic (PECL).

Summary of content (12 pages)

PAGE 1
Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663 ±15 kV ESD protection on output pins 600 Mbps (300 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential skew 700 ps maximum differential skew 1.5 ns maximum propagation delay 3.
PAGE 2
ADN4663 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 Functional Block Diagram ..............................................................
PAGE 3
ADN4663 SPECIFICATIONS VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 4
ADN4663 AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL 1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 2 Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew |tPHLD − tPLHD| 5 Channel-to-Channel Skew 6 Differential Part-to-Part Skew 7 Differential Part-to-Part Skew 8 Rise Time Fall Time Maximum Operating Frequency 9 Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL fMAX Min 0.3 0.3 0 0 0 0 0.
PAGE 5
ADN4663 Test Circuits and Timing Diagrams DOUTx+ VCC VCC RL/2 RL/2 V VOS V VOD 07927-002 DINx DOUTx– Figure 2. Test Circuit for Driver VOD and VOS DOUTx+ VCC CL SIGNAL GENERATOR DINx RL DOUTx– 50Ω 07927-003 CL CL INCLUDES LOAD AND TEST JIG CAPACITANCE. Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency 3V DINx 1.5V 1.
PAGE 6
ADN4663 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 3. Parameter VCC to GND Input Voltage (DINx) to GND Output Voltage (DOUTx+, DOUTx−) to GND Short-Circuit Duration (DOUTx+, DOUTx−) to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation SOIC Package θJA Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating −0.3 V to +4 V −0.3 V to VCC + 0.3 V −0.
PAGE 7
ADN4663 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 ADN4663 7 3 TOP VIEW (Not to Scale) DOUT1+ DIN2 6 DOUT2+ GND 4 5 DOUT2– 8 07927-005 DOUT1– VCC DIN1 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic VCC 2 3 4 5 DIN1 DIN2 GND DOUT2− 6 DOUT2+ 7 DOUT1+ 8 DOUT1− Description Power Supply Input. The part can be operated from 3.0 V to 3.6 V, and the supply should be decoupled with a 10 μF solid tantalum capacitor in parallel with a 0.
PAGE 8
ADN4663 TYPICAL PERFORMANCE CHARACTERISTICS 325.0 1.414 1.413 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV) 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) OFFSET VOLTAGE, VOS (mV) –4.1 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) 07927-008 SHORT-CIRCUIT CURRENT, I OS (mA) –4.0 3.4 3.6 400 350 300 90 1.252 3.3 3.5 TA = 25°C VCC = 3.3V TA = 25°C VIN = GND OR VCC VOUT = 0V 3.2 3.4 100 110 120 130 140 150 3.6 Figure 10.
PAGE 9
ADN4663 13 ONE CHANNEL SWITCHING 9 7 5 0.01 0.1 1 10 100 1k SWITCHING FREQUENCY (MHz) 1200 DIFFERENTIAL PROPAGATION DELAY (ns) 11.5 11.0 10.5 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) DIFFERENTIAL SKEW, tSKD1 (ps) 12 11 10 35 60 TEMPERATURE (°C) 3.5 3.6 tPLHD 1100 tPHLD 1000 100 VCC = 3.3V f = 1MHz CL = 15pF VIN = 0V TO 3V RL = 100Ω PER DRIVER –15 3.4 –20 0 20 40 60 80 100 Figure 16. Differential Propagation Delay vs. Ambient Temperature 13 10 –40 3.
PAGE 10
ADN4663 TRANSITION TIME (ps) 30 20 380 tTLH 360 tTHL 340 10 0 –40 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE, TA (°C) Figure 18. Differential Skew vs. Ambient Temperature 400 TA = 25°C f = 1MHz CL = 15pF RL = 100Ω PER DRIVER 380 tTLH 360 tTHL 340 320 3.0 3.1 3.2 3.3 3.4 3.5 POWER SUPPLY VOLTAGE, VCC (V) 320 –40 –20 0 20 40 60 80 AMBIENT TEMPERATURE, TA (°C) Figure 20. Transition Time vs. Ambient Temperature 3.6 07927-019 TRANSITION TIME (ps) VCC = 3.
PAGE 11
ADN4663 THEORY OF OPERATION When DINx is high (Logic 1), current flows out of the DOUTx+ pin (current source) through RT and back into the DOUTx− pin (current sink). At the receiver, this current develops a positive differential voltage across RT (with respect to the inverting input) and results in a Logic 1 at the receiver output. When DINx is low, DOUTx+ sinks current and DOUTx− sources current; a negative differential voltage across RT results in a Logic 0 at the receiver output.
PAGE 12
ADN4663 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.