Datasheet
Single, 3 V, CMOS, LVDS,
High Speed Differential Driver
ADN4661
Rev. 0 
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FEATURES 
±15 kV ESD protection on output pins 
600 Mbps (300 MHz) switching rates 
Flow-through pinout simplifies PCB layout 
300 ps typical differential skew 
700 ps maximum differential skew 
1.5 ns maximum propagation delay 
3.3 V power supply 
±355 mV differential signaling 
Low power dissipation: 23 mW typical 
Interoperable with existing 5 V LVDS receivers 
Conforms to TIA/EIA-644 LVDS standards 
Industrial operating temperature range (−40°C to +85°C) 
Available in surface-mount (SOIC) package 
APPLICATIONS 
Backplane data transmission 
Cable data transmission 
Clock distribution 
FUNCTIONAL BLOCK DIAGRAM 
ADN4661
V
CC
D
IN
D
OUT+
D
OUT–
GNDNC NC NC
07876-001
NC = NO CONNECT
Figure 1. 
GENERAL DESCRIPTION 
The ADN4661 is a single, CMOS, low voltage differential 
signaling (LVDS) line driver offering data rates of over 
600 Mbps (300 MHz) and ultra-low power consumption. 
It features a flow-through pinout for easy PCB layout and 
separation of input and output signals. 
The device accepts low voltage TTL/CMOS logic signals and 
converts them to a differential current output of typically 
±3.1 mA for driving a transmission medium such as a twisted-
pair cable. The transmitted signal develops a differential voltage 
of typically ±355 mV across a termination resistor at the receiv-
ing end, and this is converted back to a TTL/CMOS logic level 
by a line receiver. 
The ADN4661 and a companion LVDS receiver offer a new 
solution to high speed point-to-point data transmission, and a 
low power alternative to emitter-coupled logic (ECL) or positive 
emitter-coupled logic (PECL). 










