Datasheet

Data Sheet ADN2850
Rev. E | Page 9 of 28
PIN 1
INDICATOR
1SDO
2GND
3V
SS
4V
1
11 WP
12 PR
10 V
DD
9V
2
5
W
1
6
B1
7
B2
8
W
2
15
CLK
16
SDI
14
RDY
13
CS
A
DN2850
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
OR IS TIED TO V
SS .
TOP VIEW
(Not to Scale)
(EXPOSED
PAD)
02660-105
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 SDO
Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.
2 GND Ground Pin, Logic Ground Reference.
3 V
SS
Negative Supply. Connect to 0 V for single-supply applications. If V
SS
is used in dual supply, it must be able to sink
2 mA for 15 ms when storing data to EEMEM.
4 V1 Log Output Voltage 1. Generates voltage from an internal diode configured transistor.
5 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
6 B1 Terminal B of RDAC1.
7 B2 Terminal B of RDAC2.
8 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
9 V2 Log Output Voltage 2. Generates voltage from an internal diode configured transistor.
10 V
DD
Positive Power Supply.
11
AWP
E
Optional Write Protect. When active low, A WP
E
A
prevents any changes to the present contents, except APR
E
A
strobe.
CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie
AWP
E
A
to V
DD
, if not used.
12
APR
E
Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale until EEMEM is loaded with a new value by the user.
APR
E
A
is activated
at the logic high transition. Tie
APR
E
A
to V
DD
, if not used.
13
ACS
E
Serial Register Chip Select Active Low. Serial register operation takes place when ACS
E
A
returns to logic high.
14 RDY
Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,
Instruction 9, Instruction 10, and
APR
E
A
.
15 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
16 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
EP Exposed Pad. The exposed pad is left floating or is tied to V
SS
.