Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - Digital potentiometer logarithmic Permanent LFCSP 16 VQ

Table Of Contents

Nonvolatile Memory, Dual

1024-Position Digital Resistor

Data Sheet

ADN2850

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

FEATURES

Dual-channel, 1024-position resolution

25 kΩ, 250 kΩ nominal resistance

Maximum ±8% nominal resistor tolerance error

Low temperature coefficient: 35 ppm/°C

2.7 V to 5 V single supply or ±2.5 V dual supply

Current monitoring configurable function

SPI-compatible serial interface

Nonvolatile memory stores wiper settings

Power-on refreshed with EEMEM settings

Permanent memory write protection

Resistance tolerance stored in EEMEM

26 bytes extra nonvolatile memory for user-defined

information

1M programming cycles

100-year typical data retention

APPLICATIONS

SONET, SDH, ATM, Gigabit Ethernet, DWDM laser diode

driver, optical supervisory systems

Mechanical rheostat replacement

Instrumentation gain adjustment

Programmable filters, delays, time constants

Sensor calibration

GENERAL DESCRIPTION

The ADN2850 is a dual-channel, nonvolatile memory

, digitally

controlled resistors

with 1024-step resolution, offering

guaranteed maximum low resistor tolerance error of ±8%. The

device performs the same electronic adjustment function as a

mechanical rheostat with enhanced resolution, solid state

reliability, and superior low temperature coefficient

performance. The versatile programming of the ADN2850 via

an SPI®-compatible serial interface allows 16 modes of

operation and adjustment including scratchpad programming,

memory storing and restoring, increment/decrement, ±6 dB/step

log taper adjustment, wiper setting readback, and extra EEMEM

for user-defined information such as memory data for other

components, look-up table, or system identification

information.

FUNCTIONAL BLOCK DIAGRAM

ADDR

DECODE

ADN2850

RDAC1

SERIAL

INTERFACE

CLK

SDI

SDO

RDY

RDAC1

EEMEM1

CURRENT

MONITOR

EEMEM2

26 BYTES

RTOL*

USER EEMEM

POWER-ON

RESET

RDAC2

EEMEM

CONTROL

FULL SCALE TOLERANCE.

02660-001

GND

RDAC1

Figure 1.

In the scratchpad programming mode, a specific setting can

be programmed directly to the RDAC

resistance between Terminal W and Terminal B. This setting can

be stored into the EEMEM and is restored automatically to the

RDAC register during system power-on.

The EEMEM content can be restored dynamically or through

external

AA strobing, and a AA

AA function protects EEMEM

contents. To simplify the programming, the independent or

simultaneous linear-step increment or decrement commands

can be used to move the RDAC wiper up or down, one step at a

time. For logarithmic ±6 dB changes in the wiper setting, the

left or right bit shift command can be used to double or halve the

RDAC wiper setting.

The ADN2850 patterned resistance tolerance is stored in the

EEMEM. The actual full scale resistance can, therefore, be

known by the host processor in readback mode. The host can

execute the appropriate resistance step through a software

routine that simplifies open-loop applications as well as

precision calibration and tolerance matching applications.

The ADN2850 is available in the 5 mm × 5 mm 16-lead frame

chip scale LFCSP and thin, 16-lead TSSOP package. The part is

guaranteed to operate over the extended industrial temperature

range of −40°C to +85°C.

The terms nonvolatile memory and EEMEM are used interchangeably.

The terms digital resistor and RDAC are used interchangeably.

Summary of content (28 pages)

PAGE 1
Nonvolatile Memory, Dual 1024-Position Digital Resistor ADN2850 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION RDAC1 REGISTER CLK SDI W1 SERIAL INTERFACE SDO PR WP RDY EEMEM1 POWER-ON RESET RDAC1 B1 RDAC1 REGISTER EEMEM CONTROL W2 B2 EEMEM2 RDAC2 26 BYTES USER EEMEM I1 CURRENT MONITOR I2 VDD VSS RTOL* GND V1 V2 *RWB FULL SCALE TOLERANCE.
PAGE 2
ADN2850 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Daisy-Chain Operation ............................................................. 14 Applications ....................................................................................... 1 Terminal Voltage Operating Range ......................................... 15 General Description .........................................................................
PAGE 3
Data Sheet ADN2850 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +85°C, unless otherwise noted. These specifications apply to versions with a date code 1209 or later. Table 1.
PAGE 4
ADN2850 Parameter CURRENT MONITOR TERMINALS Current Sink at V1 Current Sink at V2 DYNAMIC CHARACTERISTICS3, 7 Resistor Noise Density Analog Crosstalk Data Sheet Symbol Conditions I1 I2 eN_WB CT Min Typ 1 0.0001 0.0001 Code= full scale RWB = 25 kΩ/250 kΩ, TA = 25°C VBX = GND, Measured VW1 with VW2 = 1 VRMS, f = 1 kHz, Code 1 = midscale, Code 2 = midscale, RWB = 25 kΩ/250 kΩ 20/64 −95/−80 Max Unit 10 10 mA mA nV/√Hz dB Typicals represent average readings at 25°C and VDD = 5 V.
PAGE 5
Data Sheet ADN2850 INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V. Table 2.
PAGE 6
ADN2850 Data Sheet Timing Diagrams CPHA = 1 CS t12 t13 t3 t1 t2 CLK CPOL = 1 t5 B23 B0 t17 t4 t7 SDI t6 HIGH OR LOW B23 (MSB) t8 t11 t10 t9 B23 (MSB) B24* SDO HIGH OR LOW B0 (LSB) B0 (LSB) t14 t15 t16 02660-002 RDY *THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE LSB OF THE CHARACTER PREVIOUSLY TRANSMITTED. THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. Figure 2.
PAGE 7
Data Sheet ADN2850 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3.
PAGE 8
ADN2850 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 RDY SDI 2 15 CS SDO 3 14 PR ADN2850 GND 4 TOP VIEW (Not to Scale) VSS 5 13 WP 12 VDD V1 6 11 V2 W1 7 10 W2 B1 8 9 B2 02660-005 CLK 1 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 Mnemonic CLK SDI SDO 4 5 GND VSS 6 7 8 9 10 11 12 13 V1 W1 B1 B2 W2 V2 VDD WP E A Description Serial Input Register Clock. Shifts in one bit at a time on positive clock edges. Serial Data Input.
PAGE 9
Data Sheet ADN2850 ADN2850 14 RDY 13 CS 15 CLK PIN 1 INDICATOR 16 SDI TOP VIEW (Not to Scale) 12 PR SDO 1 GND 2 VSS 3 (EXPOSED PAD) V1 4 11 WP 10 VDD 02660-105 B2 7 W2 8 B1 6 W1 5 9 V2 NOTES 1. THE EXPOSED PAD IS LEFT FLOATING OR IS TIED TO VSS. Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic SDO 2 3 GND VSS 4 5 6 7 8 9 10 11 V1 W1 B1 B2 W2 V2 VDD WP E A Description Serial Data Output. Serves readback and daisy-chain functions.
PAGE 10
ADN2850 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 60 0.20 +85°C +25°C –40°C 50 WIPER ON RESISTANCE (Ω) 0.15 0.10 INL ERROR (LSB) 2.7V 3.0V 3.3V 5.0V 5.5V 0.05 0 –0.05 –0.10 40 30 20 10 –0.15 200 400 600 1000 800 DIGITAL CODE 0 200 1000 3 2 0.10 IDD = 2.7V IDD = 3.3V IDD = 3.0V IDD = 5.0V IDD = 5.5V 1 0.05 IDD/ISS (µA) 0 0 –1 –0.05 –2 –0.10 0 200 400 600 1000 800 DIGITAL CODE –3 –40 02660-009 –0.15 ISS = 2.7V ISS = 3.3V ISS = 3.0V ISS = 5.0V ISS = 5.
PAGE 11
Data Sheet ADN2850 2.5982 400 VOLTAGE (V) 200 100 1 2 3 4 5 2.5873 –19.8 –10 VDIO (V) Figure 12. IDD vs Digital Input Voltage 20 30 40 50 60 70 80 Figure 15. Midscale Glitch Energy, RAB = 25 kΩ, Code 0x200 to Code 0x1FF 2.2492 2.2490 VDD = 5V ± 10% AC VSS = 0V, IW (25k) = 200µA –10 I (250k) = 20µA, V = 0V W B MEASURED AT VW WITH CODE = 0x200 –20 TA = 25°C 2.2485 2.2480 2.2475 2.2470 RAB = 250kΩ VOLTAGE (V) –30 RAB = 25kΩ –40 –50 2.2465 2.2460 2.2455 2.2450 2.
PAGE 12
ADN2850 Data Sheet 100 TA = 25°C THEORECTICAL (IWB_MAX – mA) CLK (5V/DIV) SDI (5V/DIV) 1 RWB = 25kΩ 0.1 RWB = 250kΩ 0.01 02660-023 IDD (2mA/DIV) 10 0 128 256 384 512 640 768 896 CODE (Decimal) Figure 18. IDD vs. Time when Storing Data to EEMEM Figure 19. IWB_MAX vs. Code TEST CIRCUITS Figure 20 to Figure 24 define the test conditions used in the Specifications section. DUT RSW = DUT IW W 0.1V ISW W + B B 02660-026 VMS 0.1V ISW – Figure 20.
PAGE 13
Data Sheet ADN2850 THEORY OF OPERATION The ADN2850 digital programmable resistor is designed to operate as a true variable resistor. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register, allowing unlimited changes of resistance settings. The scratchpad register can be programmed with any position setting using the standard SPI serial interface by loading the 24-bit data-word.
PAGE 14
ADN2850 Data Sheet EEMEM PROTECTION VDD The write protect (WP) pin disables any changes to the scratchpad register contents, except for the EEMEM setting, which can still be restored using Instruction 1, Instruction 8, and the PR pulse. Therefore, WP can be used to provide a hardware EEMEM protection feature. E A A E A INPUT 300Ω WP E A A A All digital inputs are ESD protected, high input impedance that can be driven directly from most digital sources.
PAGE 15
Data Sheet ADN2850 resistor and the capacitive loading at the SDO-to-SDI interface may require additional time delay between subsequent devices. When two ADN2850s are daisy-chained, 48 bits of data are required. The first 24 bits (formatted 4-bit command, 4-bit address, and 16-bit data) go to U2, and the second 24 bits with the same format go to U1. Keep CS low until all 48 bits are clocked into their respective serial registers. CS is then pulled high to complete the operation.
PAGE 16
ADN2850 Data Sheet In Table 7, command bits are C0 to C3, address bits are A0 to A3, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are applicable to EEMEM. Table 7. 24-Bit Serial Data-Word RDAC EEMEM MSB C3 C2 C3 C2 C1 C1 Command Byte 0 C0 0 0 0 C0 A3 A2 A1 A0 A0 X D15 X D14 X D13 Data Byte 1 X X D12 D11 X D10 D9 D9 D8 D8 D7 D7 D6 D6 Data Byte 0 D5 D4 D3 D5 D4 D3 D2 D2 D1 D1 LSB D0 D0 Command instruction codes are defined in Table 8. Table 8.
PAGE 17
Data Sheet ADN2850 ADVANCED CONTROL MODES the RDAC register is then set to Code 1. Similarly, if the data in the RDAC register is greater than or equal to midscale and the data is shifted left, then the data in the RDAC register is automatically set to full scale. This makes the left-shift function as ideal a logarithmic adjustment as possible.
PAGE 18
ADN2850 Data Sheet For example, if RWB_RATED = 250 kΩ and the data in the SDO shows XXXX XXXX 1001 1100 0000 1111, RWB at full scale can be calculated as follows: Using CS to Re-Execute a Previous Command Another subtle feature of the ADN2850 is that a subsequent CS strobe, without clock and data, repeats a previous command. E A MSB: 1 = positive Next 7 LSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 × 2−8 = 0.06 % tolerance = 28.06% Therefore, RWB at full scale = 320.
PAGE 19
Data Sheet ADN2850 PROGRAMMING THE VARIABLE RESISTOR The nominal resistance of the RDAC between Terminal W and Terminal B, RWB, is available with 25 kΩ and 250 kΩ with 1024 positions (10-bit resolution). The final digits of the part number determine the nominal resistance value, for example, 25 kΩ = 24.4 Ω; 250 kΩ = 244 Ω. The 10-bit data-word in the RDAC latch is decoded to select one of the 1024 possible settings.
PAGE 20
ADN2850 Data Sheet Table 17. Using Left-Shift by One to Increment 6 dB Steps Table 19. Reading Back Data from Memory Locations SDI 0xC0XXXX SDO 0xXXXXXX SDI 0x92XXXX SDO 0xXXXXXX 0x00XXXX 0x92AAAA 0xC1XXXX 0xC0XXXX Action Moves Wiper 1 to double the present data contained in the RDAC1 register. Moves Wiper 2 to double the present data contained in the RDAC2 register. Action Prepares data read from USER1 EEMEM location.
PAGE 21
Data Sheet ADN2850 APPLICATIONS INFORMATION C1 GAIN CONTROL COMPENSATION A digital resistor is commonly used in gain control such as the noninverting gain amplifier shown in Figure 34. C2 2.2pF +2.5V R1 R2 B VI W R2 250kΩ B V+ W AD8601 R R B C2 U1 ADJUSTED CONCURRENTLY VO VI Figure 35. Sallen-Key Low-Pass Filter 02660-047 C1 11pF –2.5V 02660-055 W The design equations are Figure 34.
PAGE 22
ADN2850 Data Sheet At the resonant frequency, fO, the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. With R = R', VCC C = C', and R2 = R2A /(R2B + RDIODE), the oscillation frequency is CS CONTROL RDAC1 B2 EEMEM W2 At resonance, setting R2/R1 = 2 balances the bridge. In practice, R2/R1 should be set slightly larger than 2 to ensure that the oscillation can start.
PAGE 23
Data Sheet ADN2850 0.30 V2 – V1 (V) 0.25 (VT = 26 mV @ 25°C) k is the Boltzmann’s constant, 1.38e-23 Joules/Kelvin. q is the electron charge, 1.6e-19 coulomb. T is the temperature in Kelvin. IPD is the photodiode current. IREF is the reference current. 0.20 6 0.15 3 0.10 0 0.05 –3 Figure 38 shows a conceptual circuit. 0 0.1µ –6 1µ 10µ POST AMP TIA LPF 0.75 BIT RATE 9 ERROR APPROXIMATING ERROR (%) IS1 and IS2 are saturation current.
PAGE 24
ADN2850 Data Sheet RDAC CIRCUIT SIMULATION MODEL In operation, such as gain control, the tolerance mismatch between the digital resistor and the discrete resistor can cause repeatability issues among various systems (see Figure 42). Because of the inherent matching of the silicon process, it is practical to apply the dual-channel device in this type of application. As such, R1 can be replaced by one of the channels of the digital resistor and programmed to a specific value.
PAGE 25
Data Sheet ADN2850 OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 0.60 MAX 2.40 REF 0.60 MAX 13 1 12 0.80 BSC 4.75 BSC SQ 3.25 3.10 SQ 2.95 EXPOSED PAD 9 0.75 0.60 0.50 TOP VIEW 1.00 0.85 0.80 4 8 BOTTOM VIEW 0.80 MAX 0.65 TYP 12° MAX 0.35 0.30 0.25 SEATING PLANE 5 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.
PAGE 26
ADN2850 Data Sheet NOTES Rev.
PAGE 27
Data Sheet ADN2850 NOTES Rev.