Datasheet

Data Sheet ADN2850
Rev. E | Page 5 of 28
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both V
DD
= 3 V and V
DD
= 5 V.
Table 2.
Parameter Symbol Conditions Min Typ
1
Max Unit
Clock Cycle Time (t
CYC
) t
1
20 ns
EE
AA Setup Time
CS
t
2
10 ns
CLK Shutdown Time to AA
CS
EE
AA Rise t
3
1 t
CYC
Input Clock Pulse Width
t
4
, t
5
Clock level high or low
10
ns
Data Setup Time t
6
From positive CLK transition 5 ns
Data Hold Time t
7
From positive CLK transition 5 ns
AA
CS
EE
AA to SDO-SPI Line Acquire t
8
40 ns
AA
CS
EE
AA to SDO-SPI Line Release t
9
50 ns
CLK to SDO Propagation Delay
10F
2
t
10
R
P
= 2.2 kΩ, C
L
< 20 pF
50
ns
CLK to SDO Data Hold Time
t
11
R
P
= 2.2 kΩ, C
L
< 20 pF
0
ns
AA
CS
EE
AA High Pulse Width11F
3
t
12
10 ns
AA
CS
EE AAHigh to AA
CS
EE
AA High
3
t
13
4 t
CYC
RDY Rise to AA
CS
EE
AA Fall t
14
0 ns
AA
CS
EE
AA Rise to RDY Fall Time t
15
0.15 0.3 ms
Store EEMEM Time
12F
4,
13F
5
t
16
Applies to instructions 0x2, 0x3 15 50 ms
Read EEMEM Time
4
t
16
Applies to instructions 0x8, 0x9, 0x10
7
30
µs
AA
CS
EE
AA Rise to Clock Rise/Fall Setup t
17
10 ns
Preset Pulse Width (Asynchronous)
14F
6
t
PRW
50 ns
Preset Response Time to Wiper Setting
6
t
PRESP
AA
PR
EE
AA
pulsed low to refresh wiper positions
30 µs
Power-On EEMEM Restore Time
6
t
EEMEM
30 µs
FLASH/EE MEMORY RELIABILITY
Endurance
15F
7
T
A
= 25°C 1 MCycles
100 kCycles
Data Retention
16F
8
100
Years
1
Typicals represent average readings at 25°C and V
DD
= 5 V.
2
Propagation delay depends on the value of V
DD
, R
PULL-UP
, and C
L
.
3
Valid for commands that do not activate the RDY pin.
4
RDY pin low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the
PR
hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;
CMD_2, CMD_3 ~ 15 ms,
PR
hardware pulse ~ 30 µs.
5
Store EEMEM time depends on the temperature and EEMEM write cycles. Higher timing is expected at lower temperature and higher write cycles.
6
Not shown in Figure 2 and Figure 3.
7
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.
8
Retention lifetime equivalent at junction temperature (T
J
) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.