Datasheet

ADN2817/ADN2818 Data Sheet
Rev. E | Page 6 of 40
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter Conditions Min Typ Max Unit
CML OUPUT CHARACTERISTICS (CLKOUTP/CLKOUTN,
DATAOUTP/DATAOUTN)
Single-Ended Output Swing, V
SE
See Figure 3 300 350 600 mV
Differential Output Swing, V
DIFF
See Figure 3 600 700 1200 mV
Output Voltage
High, V
OH
VCC V
Low, V
OL
VCC − 0.6
VCC − 0.35
VCC − 0.3
V
CML Outputs Timing
Rise Time 20% to 80% 80 112 ps
Fall Time 80% to 20% 80 123 ps
Setup Time, t
S
See Figure 2, OC-48 150 200 250 ps
Hold Time, t
H
See Figure 2, OC-48 150 200 250 ps
Setup Time, t
DDRS
See Figure 4, OC-48 140 170 200 ps
Hold Time, t
DDRH
See Figure 4, OC-48 200 230 260 ps
I
2
C INTERFACE DC CHARACTERISTICS
LVCMOS
Input Voltage
High, V
IH
0.7 VCC V
Low, V
IL
0.3 VCC V
Input Current V
IN
= 0.1 VCC or V
IN
= 0.9 VCC −10.0 +10.0 µA
Output Low Voltage V
OL
, I
OL
= 3.0 mA 0.4 V
I
2
C INTERFACE TIMING See Figure 22
SCK Clock Frequency 400 kHz
SCK Pulse Width High
High, t
HIGH
600 ns
Low, t
LOW
1300 ns
Start Condition
Hold Time, t
HD;STA
600 ns
Setup Time, t
SU;STA
600 ns
Data
Setup Time, t
SU;DAT
100 ns
Hold Time, t
HD;DAT
300 ns
SCK/SDA Rise/Fall Time, t
R
/t
F
20 + 0.1 Cb 300 ns
Stop Condition Setup Time, t
SU;STO
600 ns
Bus Free Time Between a Stop and a Start, t
BUF
1300 ns
REFCLK CHARACTERISTICS Optional lock to REFCLK mode
Input Voltage Range At REFCLKP or REFCLKN
V
IL
0 V
V
IH
VCC V
Minimum Differential Input Drive 100 mV p-p
Reference Frequency 10 200 MHz
Required Accuracy 100 ppm