Datasheet

ADN2817/ADN2818 Data Sheet
Rev. E | Page 30 of 40
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
For best practice, the use of one low impedance ground plane is
recommended. To reduce series inductance, solder the VEE pins
directly to the ground plane. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. Connect the exposed pad to the ground
plane using plugged vias so that solder does not leak through
the vias during reflow.
Use of a 10 µF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply (VCC and VEE),
as close as possible to the ADN2817/ADN2818 VCC pins.
If connections to the supply and ground are made through
vias, the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/DATAOUTN
output buffers. See the schematic in Figure 36 for recommended
connections.
By using adjacent power supply and ground planes, excellent
high frequency decoupling can be realized by using close
spacing between the planes. This capacitance is given by
C
PLANE
= 0.88ε
r
A/d (pF)
where:
ε
r
is the dielectric constant of the PCB material.
A is the area of the overlap of power and ground planes (cm
2
).
d is the separation between planes (mm).
For FR-4, ε
r
= 4.4 and 0.25 mm spacing, C ≈ 15 pF/cm
2
.
VBER
32
VCC
31
VEE
30
DATAOUTP
29
DATAOUTN
28
SQUELCH
27
CLKOUTP
26
CLKOUTN
25
THRADJ
R
TH
9
REFCLKP
10
REFCLKN
11
VCC
12
VEE
13
CF2
14
CF1
15
LOL
16
BERMODE
1
VCC
2
VREF
3
NIN
4
PIN
5
SLICEP
6
SLICEN
7
VEE
8
VCC
24
VEE
23
LOS
22
SDA
21
SCK
EXPOSED PAD
TIED OFF TO VEE
PLANE WITH VIAS.
20
SADDR5
19
VCC
18
VEE
17
ADN2817/
ADN2818
TOP VIEW
(Not to Scale)
1nF0.1µF
VCC
0.47µF +20%
>300MΩ
INSULATION RESISTANCE
µC
I
2
C CONTROLLER
µC
VCC
VCC
1nF
0.1µF
1nF
0.1µF
C
IN
VCC
TIA
50Ω
50Ω
1nF0.1µF
0.1µF
DATAOUTP
DATAOUTN
CLKOUTP
CLKOUTN
50Ω TRANSMISSION
LINES
VCC
4 × 100Ω
1nF
0.1µF
+
VCC
10µF
06001-025
10k
Ω
10kΩ
Figure 36. Typical ADN2817/ADN2818 Applications Circuit