Datasheet

Data Sheet ADN2817/ADN2818
Rev. E | Page 15 of 40
Table 8. Internal Register Map
1
Reg Name R/W Addr D7 D6 D5 D4 D3 D2 D1 D0
FREQ0 R 0x00 MSB LSB
FREQ1 R 0x01 MSB LSB
FREQ2 R 0x02 0 MSB LSB
Rate R 0x03 COARSE_RD[8:1]
MISC R 0x04 X X LOS status Static
LOL
LOL status Data rate
measurement
complete
X COARSE_RD[0]
(LSB)
CTRLA W 0x08 f
REF
range Data rate/DIV_FREF ratio Measure
data rate
Lock to REFCLK
CTRLA_RD R 0x05 Readback CTRLA
CTRLB W 0x09 Config
LOL
Reset
MISC[4]
Initiate freq
acquisition
0 Reset
MISC[2]
0 0 0
CTRLB_RD R 0x06 Readback CTRLB
CTRLC W 0x11 0 0 0 0 0 Config LOS Squelch
mode
0
CTRLD
W
0x22
CDR
bypass
Disable
DATAOUT
buffer
Disable
CLKOUT
buffer
0
Initiate
PRBS
sequence
PRBS mode
CTRLE/BERCTLB
2
W 0x1F 0 0 Enable
BERMON
BER
stdby
mode
0 PRBS/DDR enable and output mode
SEL_MODE W 0x34 0 0 0 0 Limited
rate mode
0 CLK
holdover
mode
0
HI_CODE W 0x35 HI_CODE[8:1]
LO_CODE W 0x36 LO_CODE[8:1]
CODE_LSB W 0x39 0 0 0 0 0 0 HI_CODE[0]
(LSB)
LO_CODE[0]
(LSB)
BERCTLA
W
0x1E
BER timer (NUMBITS)
0
BER start
pulse
Error count byte select, for example, 011 = Byte 3
of 5 (NUMERRORS[39:0])
BERSTS R 0x20 X X X X X X X End of BER
measurement
(EOBM)
BER_RES R 0x21 BER_RES[7:0], one byte of pseudo BER measurement result (NUMERRORS[39:0])
BER_DAC R 0x24 X X BER_DAC[5:0], input to BER DAC in analog BERMON mode
Phase W 0x37 0 0 Phase[5:0], twos complement sample phase adjustment,
phase code range is from −30 decimal to +30 decimal,
which gives a sampling phase offset range from −0.5 UI to +0.5 UI;
for example, phase = 111010 is−6 decimal,
which gives a sampling phase offset of −6/+60 = −0.1 UI
1
X = don’t care.
2
Both CTRLE and BERCTLB registers are used, depending on the application.
Table 9. Miscellaneous Register, MISC
LOS Status Static LOL LOL Status
Data Rate Measurement
Complete
COARSE_RD[0]
(LSB)
D7 D6 D5 D4 D3 D2 D1 D0
X
X
0 = no loss of signal
0 = waiting for next LOL
0 = locked
0 = measuring data rate
X
COARSE_RD[0]
1 = loss of signal 1 = static LOL until reset 1 = acquiring 1 = measurement complete