Datasheet

ADN2814 Data Sheet
Rev. C | Page 10 of 28
I
2
C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
1A500000X
MSB = 1 SET BY
PIN 19
0 = WR
1 = RD
SLAVE ADDRESS [6...0]
R/W
CTRL.
04949-007
Figure 7. Slave Address Configuration
S SLAVE ADDR, LSB = 0 (WR) A(S) A(S) A(S)DATASUB ADDR A(S) PDATA
04949-00
8
Figure 8. I
2
C Write Data Transfer
S
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(M) = LACK OF ACKNOWLEDGE BY MASTER
SSLAVE ADDR, LSB = 0 (WR) SLAVE ADDR, LSB = 1 (RD)A(S) A(S)SUB ADDR A(S) DATA A(M) DATA PA(M)
04949-009
Figure 9. I
2
C Read Data Transfer
START BIT
S
STOP BIT
P
ACKACKWR ACK
D0D7A0A7A5A6
SLADDR[4...0]
SLAVE ADDRESS SUB ADDRESS DATA
SUB ADDR[6...1] DATA[6...1]
SCK
SDA
04949-010
Figure 10. I
2
C Data Transfer Timing
t
BUF
SDA
SS
SCK
t
F
t
LOW
t
R
t
F
t
HD;STA
t
HD;DAT
t
SU;DAT
t
HIGH
t
SU;STA
t
SU;STO
t
HD;STA
t
R
04949-011
PS
Figure 11. I
2
C Port Timing Diagram