Datasheet

Data Sheet ADN2812
Rev. E | Page 21 of 28
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return
for the output buffers. The exposed pad should be connected
to the GND plane using plugged vias so that solder does not
leak through the vias during reflow.
Use of a 10 µF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply VCC and VEE
and as close as possible to the ADN2812 VCC pins.
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series induc-
tance, especially on Pin 24, which supplies power to the high
speed CLKOUTP/CLKOUTN and DATAOUTP/DATAOUTN
output buffers. Refer to the schematic in Figure 24 for recom-
mended connections.
By using adjacent power supply and GND planes, excellent high
frequency decoupling can be realized by using close spacing
between the planes. This capacitance is given by
( )
pFε88.0 A/dC
r
plane
=
where:
ε
r
is the dielectric constant of the PCB material.
A is the area of the overlap of power and GND planes (cm
2
).
d is the separation between planes (mm).
For FR-4, ε
r
= 4.4 and 0.25 mm spacing, C ~15 pF/cm
2
.
04228-024
R
TH
NC
NC = NO CONNECT
1
2
3
4
5
6
7
8
VCC
VCC
VREF
NIN
PIN
SLICEP
SLICEN
VEE
VCC
50Ω
TRANSMISSION LINES
100Ω × 4
VCC
VEE
LOS
SDA
SCK
SADDR5
VCC
VEE
VCC VCC VEE DATAOUTP DATAOUTN SQUELCH CLKOUTP CLKOUTN
THRADJ
REFCLKP
REFCLKN
VCC
VEE
CF2 CF1
LOL
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
EXPOSED PAD
TIED OFF TO
VEE PLANE
WITH VIAS
CLKOUTN
CLKOUTP
DATAOUTN
DATAOUTP
VCC
TIA
50Ω
50Ω
C
IN
C
IN
1nF0.1µF
0.1µF
10µF
+
0.1µF 1nF
VCC
VCC
VCC
µC
µC
I
2
C
CONTROLLER
0.1µF1nF
0.1µF
VCC
1nF
0.1µF
0.47µF ± 20% >300MΩ
INSULATION RESISTANCE
1nF
Figure 24. Typical Applications Circuit