Datasheet

ADN2812 Data Sheet
Rev. E | Page 10 of 28
I
2
C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
04228-007
1 A5 0 0 0 0 0 X
MSB = 1 SET BY
PIN 19
0 = WR
1 = RD
SLAVE ADDRESS [6:0]
R/W
CTRL.
Figure 7. Slave Address Configuration
04228-008
S SLAVE ADDR, LSB = 0 (WR) A(S) A(S) A(S)DATASUB ADDR
A(S) PDATA
Figure 8. I
2
C Write Data Transfer
04228-009
S
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(M) = LACK OF ACKNOWLEDGE BY MASTER
SSLAVE
ADDR, LSB = 0 (WR) SLAVE ADDR, LSB = 1 (RD)A(S) A(S)SUB ADDR A(S) DATA A(M) DATA P
A(M)
Figure 9. I
2
C Read Data Transfer
04228-010
START BIT
S
STOP BIT
P
ACKACKWR ACK
D0D7A0A7A5A6
SLADDR[4...0]
SLAVE ADDRESS SUB ADDRESS DATA
SUB ADDR[6:1] DATA[6:1]
SCK
SDA
Figure 10. I
2
C Data Transfer Timing
04228-011
t
BUF
SDA
S S P S
SCK
t
F
t
LOW
t
R
t
F
t
HD;STA
t
HD;DAT
t
SU;DAT
t
HIGH
t
SU;STA
t
SU;STO
t
HD;STA
t
R
Figure 11. I
2
C Port Timing Diagram