Datasheet

Data Sheet ADN2805
Rev. B | Page 9 of 16
Table 7. Internal Register Map
1, 2
Reg. Name R/W Address D7 D6 D5 D4 D3 D2 D1 D0
FREQ0 R 0x0 MSB LSB
FREQ1 R 0x1 MSB LSB
FREQ2 R 0x2 0 MSB LSB
RATE R 0x3 COARSE_RD[8] MSB Coarse Data Rate Readback COARSE_RD[1]
MISC R 0x4 X X X
Static
LOL
LOL
Status
Data Rate
Measure
Complete
X
COARSE_RD[0]
(LSB)
CTRLA W 0x8 f
REF
Range Data Rate/DIV_f
REF
Ratio Measure Data Rate Lock to Reference
CTRLB W 0x9
Config
LOL
Reset
MISC[4]
System
Reset
0
Reset
MISC[2]
0 0 0
CTRLC W 0x11 0 0 0 0 0 0 Squelch Mode Output Boost
1
All writeable registers default to 0x00.
2
X = don’t care.
Table 8. Miscellaneous Register, MISC
1
Static LOL LOL Status Data Rate Measurement Complete Coarse Rate Readback LSB
D7 D6 D5 D4 D3 D2 D1 D0
X X X 0 = waiting for next LOL 0 = locked 0 = measuring data rate X COARSE_RD[0]
1 = static LOL until reset 1 = acquiring 1 = measurement complete
1
X = don’t care.
Table 9. Control Register, CTRLA
1
f
REF
Range Data Rate/DIV_f
REF
Ratio Measure Data Rate Lock to Reference
D7 D6 D5 D4 D3 D2 D1 D0
0 0 10 MHz to 20 MHz 0 0 0 0 1 Set to 1 to measure data rate 0 = lock to input data
0 1 20 MHz to 40 MHz 0 0 0 1 2 1 = lock to reference clock
1 0 40 MHz to 80 MHz 0 0 1 0 4
1 1 80 MHz to 160 MHz n 2
n
1 0 0 0 256
1
Where DIV_f
REF
is the divided down reference referred to the 10 MHz to 20 MHz band.
Table 10. Control Register, CTRLB
Configure LOL Reset MISC[4] System Reset Reset MISC[2]
D7 D6 D5 D4 D3 D2 D1 D0
0 = LOL pin normal operation
1 = LOL pin is static LOL
Write a 1 followed by
0 to reset MISC[4]
Write a 1 followed by
0 to reset ADN2805
Set to 0
Write a 1 followed by
0 to reset MISC[2]
Set to 0 Set to 0 Set to 0
Table 11. Control Register, CTRLC
Squelch Mode Output Boost
D7 D6 D5 D4 D3 D2 D1 D0
0 = SQUELCH DATAOUT and CLKOUT 0 = default output swing Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0
1 = SQUELCH DATAOUT or CLKOUT 1 = boost output swing