Datasheet

ManualsBrandsANALOG DEVICES ManualsClock & Timing ICsLFCSP-32-VQ

1.25 Gbps Clock and Data Recovery IC

Data Sheet

ADN2805

Rev. B

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FEATURES

Locks to 1.25 Gbps NRZ serial data input

Patented clock recovery architecture

No reference clock required

Loss-of-lock indicator

C interface to access optional features

Single-supply operation: 3.3 V

Low power: 390 mW typical

5 mm × 5 mm 32-lead LFCSP, Pb free

APPLICATIONS

GbE line card

GENERAL DESCRIPTION

The ADN2805 provides the receiver functions of quantization

and clock and data recovery for 1.25 Gbps. The ADN2805

automatically locks to all data rates without the need for an

external reference clock or programming. All SONET jitter

requirements are met, including jitter transfer, jitter generation,

and jitter tolerance.

All specifications are specified for −40°C to +85°C ambient

temperature, unless otherwise noted. The ADN2805 is available

in a compact 5 mm × 5 mm 32-lead LFCSP.

FUNCTIONAL BLOCK DIAGRAM

LOL

DATAOUTP/

DATAOUTN

ADN2805

CLKOUTP/

CLKOUTN

VCC VEECF1 CF2

NIN

VREF

BUFFER

VCO

PHASE

SHIFTER

PHASE

DETECT

FREQUENCY

DETECT

DATA

RE-TIMING

LOOP

FILTER

LOOP

FILTER

REFCLKP/REFCLKN

(OPTIONAL)

07121-001

Figure 1.

Summary of content (16 pages)

PAGE 1
.25 Gbps Clock and Data Recovery IC ADN2805 Data Sheet FEATURES GENERAL DESCRIPTION Locks to 1.25 Gbps NRZ serial data input Patented clock recovery architecture No reference clock required Loss-of-lock indicator I2C interface to access optional features Single-supply operation: 3.3 V Low power: 390 mW typical 5 mm × 5 mm 32-lead LFCSP, Pb free The ADN2805 provides the receiver functions of quantization and clock and data recovery for 1.25 Gbps.
PAGE 2
ADN2805 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 10 Applications....................................................................................... 1 Functional Description.................................................................. 12 General Description .......................................................
PAGE 3
Data Sheet ADN2805 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 1.
PAGE 4
ADN2805 Data Sheet OUTPUT AND TIMING SPECIFICATIONS Table 3.
PAGE 5
Data Sheet ADN2805 Timing Characteristics CLKOUTP TH 07121-002 TS DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP/N VOH VOS 07121-003 |VOD| VOL Figure 3. Differential Output Specifications 5mA RLOAD 100Ω 100Ω VDIFF SIMPLIFIED LVDS OUTPUT STAGE Figure 4. Differential Output Stage Rev.
PAGE 6
ADN2805 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted. Thermal Resistance 4-layer board with exposed paddle soldered to VEE. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Range Rating 4.2 V VEE − 0.4 V VCC + 0.4 V 125°C −65°C to +150°C Table 5.
PAGE 7
Data Sheet ADN2805 32 VCC 31 VCC 30 VEE 29 DATAOUTP 28 DATAOUTN 27 SQUELCH 26 CLKOUTP 25 CLKOUTN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDIC ATOR ADN2805* TOP VIEW (Not to Scale) 24 VCC 23 VEE 22 NC 21 SDA 20 SCK 19 SADDR5 18 VCC 17 VEE * THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. 07121-005 NC 9 REFCLKP 10 REFCLKN 11 VCC 12 VEE 13 CF2 14 CF1 15 LOL 16 VCC 1 VCC 2 VREF 3 NIN 4 PIN 5 NC 6 NC 7 VEE 8 Figure 5. Pin Configuration Table 6.
PAGE 8
ADN2805 Data Sheet I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION R/W CTRL. SLAVE ADDRESS [6...0] A5 SET BY PIN 19 0 0 0 0 0 X 07121-006 1 MSB = 1 0 = WR 1 = RD S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P 07121-007 Figure 6. Slave Address Configuration Figure 7.
PAGE 9
Data Sheet ADN2805 Table 7. Internal Register Map 1, 2 Reg.
PAGE 10
ADN2805 Data Sheet THEORY OF OPERATION Another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second-order phase-locked loop, and this zero is placed in the feedback path and, thus, does not appear in the closed-loop transfer function. Jitter peaking in a conventional second-order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function.
PAGE 11
Data Sheet ADN2805 The gain of the loop integrator is small for high jitter frequencies; therefore, larger phase differences are needed to make the loop control voltage large enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the integrator determines the jitter accommodation. Because the gain of the loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency.
PAGE 12
ADN2805 Data Sheet FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION When LOL deasserts, the FLL turns off. The PLL/DLL pulls in the VCO frequency until the VCO frequency equals the data frequency. The frequency loop requires a single external capacitor between CF1 and CF2, Pin 15 and Pin 14. A 0.47 μF ± 20%, X7R ceramic chip capacitor with <10 nA leakage current is recommended. Calculate the leakage current of the capacitor by dividing the maximum voltage across the 0.
PAGE 13
Data Sheet ADN2805 SQUELCH MODE Two squelch modes are available with the ADN2805. The SQUELCH DATAOUT and CLKOUT mode is selected when CTRLC[1] = 0 (default mode). In this mode, when the SQUELCH input, Pin 27, is driven to a TTL high state, both the clock and data outputs are set to the zero state to suppress downstream processing. If the squelch function is not required, tie Pin 27 to VEE. SQUELCH DATAOUT or CLKOUT mode is selected when CTRLC[1] is 1.
PAGE 14
ADN2805 Data Sheet APPLICATIONS INFORMATION PCB DESIGN GUIDELINES If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pin 24, which supplies power to the high speed CLKOUTP/CLKOUTN and DATAOUTP/ DATAOUTN output buffers. Refer to Figure 14 for the recommended connections. Proper RF PCB design techniques must be used for optimal performance.
PAGE 15
Data Sheet ADN2805 VCC Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN, if a high frequency reference clock is used, such as 155 MHz). It is also necessary for the PIN/NIN input traces to be matched in length, and the CLKOUTP/ CLKOUTN and DATAOUTP/DATAOUTN output traces to be matched in length to avoid skew between the differential traces.
PAGE 16
ADN2805 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 17.