Datasheet

REV. B

ADMC401

–58–

SPORT0_AUTOBUF_CTRL (R/W)

1514131211109876543210

0000 00

RBUF

RECEIVE AUTOBUFFERING ENABLE

TBUF

TRANSMIT AUTOBUFFERING ENABLE

RMREG

RECEIVE AUTOBUFFER M REGISTER

RIREG

RECEIVE AUTOBUFFER I REGISTER

CLKODIS

CLKOUT DISABLE CONTROL BIT

BIASRND

MAC BIASED ROUNDING CONTROL BIT

TIREG

TRANSMIT AUTOBUFFER I REGISTER

TMREG

TRANSMIT AUTOBUFFER MREGISTER

DM (0x3FF3)

SPORT0_SCLKDIV (R/W)

SPORT0_RFSDIV (R/W)

1514131211109876543210

DM (0x3FF4)

DM (0x3FF5)

Figure 46. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.