Datasheet

REV. B
ADMC401
–56–
DM (0x3FFC)
TPERIOD (R/W)
TCOUNT (R/W)
TSCALE (R/W)
DM (0x3FFD)
DM (0x3FFB)
1514131211109876543210
00000000
SSTAT (R)
PC STACK EMPTY
PC STACK OVERFLOW
COUNT STACK EMPTY
COUNT STACK OVERFLOW
STATUS STACK EMPTY
STATUS STACK OVERFLOW
LOOP STACK EMPTY
LOOP STACK OVERFLOW
76543210
10101010
MSTAT (R/W)
6543210
0000000
DSP REGISTER
DATA REGISTER BANK SELECT
0 = PRIMARY, 1 = SECONDARY
BIT REVERSE MODE ENABLE (DAG1)
ALU OVERFLOW LATCH MODE ENABLE
AR SATURATION MODE ENABLE
MAC RESU PLACEMENT
0 = FRACTIONAL,LT 1 = INTERGER
TIMER ENABLE
GO MODE ENABLE
SYSCNTL (R/W)
PWAIT
PROGRAM MEMORY
WAIT STATES
1514131211109876543210
BPAGE
BOOT PAGE SELECT
BWAIT
BOOT WAIT STATES
BFORCE
BOOT FORCE BIT
SPORT0 ENABLE
1 = ENABLE, 0 = DISABLED
10100000 11111000
DM (0x3FFF)
SPORT1 ENABLE
1 = ENABLE, 0 = DISABLED
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = FI, FO, IRQ0, IRQ1, SCLK
AZ ALU RESULT ZERO
AN ALU RESULT NEGATIVE
AV ALU OVERFLOW
AC ALU CARRY
AS ALU X INPUT SIGN
AQ ALU QUOTIENT
MV MAC OVERFLOW
SS SHIFTER INPUT SIGN
76543210
ASTAT (R/W)
00000000
DSP REGISTER
DSP REGISTER
Figure 44 Structure of Registers of ADMC401
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.