Datasheet

REV. B

ADMC401

–54–

MODECTRL (R/W)

DM (0x2015)

DATA RECEIVE

SELECT

1 = DR1B

0 = DR1A

1 = UART MODE

0 = SPORT MODE

SPORT1

MODE

SYSSTAT (R)

DM (0x2016)

1 = HI

0 = LO

1 = WATCHDOG TRIP

0 = NO WATCHDOG TRIP

PWMTRIP

PIN STATE

WATCHDOG

FLAG

PWMPOL

PIN STATE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000

PWM PHASE

FLAG

1 = SECOND HALF CYCLE

0 = FIRST HALF CYCLE

PWM

MODE

1 = DOUBLE UPDATE

0 = SINGLE UPDATE

AUXILIARY

PWM MODE

1 = INDEPENDENT

0 = OFFSET

1 = HI => ACTIVE HI

0 = LO => ACTIVE LO

00000000 0000

000000000000

Figure 42. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.